Abstract: A dual-edge modulation controller including first and second ramp circuits, first and second comparators, an error amplifier and pulse control logic. The first ramp circuit provides a leading-edge ramp synchronous with a clock. The error amplifier compares a feedback signal with a reference and provides a compensation signal. The first comparator compares the leading-edge ramp with the compensation signal and asserts a set signal. The second ramp circuit provides a trailing-edge ramp that begins ramping when the set signal is asserted. The second comparator compares the trailing-edge ramp with the compensation signal and asserts a reset signal. The pulse control logic asserts a PWM signal when the set signal is asserted and de-asserts the PWM signal when the reset signal is asserted. The controller may control multiple phases with current balancing. The slew rate of the ramps may be adjusted based on the number of PWM signal asserted.

Abstract: A phase removal control system for a multiphase DC/DC converter including combination logic, disable logic, and a current detector. The multiphase DC/DC converter includes first and second output phase circuits and a controller providing first and second PWM signals for the first and second output phase circuits, respectively. The combination logic combines the second PWM signal with the first PWM signal when a phase enable signal is de-asserted and while a current detect signal indicates current above a predetermined minimum current level. The disable logic passes the second PWM signal to the second output phase circuit when the phase enable signal is asserted and blocks the second PWM signal from the second output phase circuit when the phase enable signal is de-asserted. The current detector has an input for sensing current through the second output phase circuit and an output providing the current detect signal indicative thereof.

Abstract: Apparatus and Methods for the self-alignment of separated regions in a lateral MOSFET of an integrate circuit. In one embodiment, a method comprising, forming a relatively thin dielectric layer on a surface of a substrate. Forming a first region of relatively thick material having a predetermined lateral length on the surface of the substrate adjacent the relatively thin dielectric layer. Implanting dopants to form a top gate using a first edge of the first region as a mask to define a first edge of the top gate. Implanting dopants to form a drain contact using a second edge of the first region as a mask to define a first edge of the drain contact, wherein the distance between the top gate and drain contact is defined by the lateral length of the first region.

Abstract: Provided herein are self-calibrating timing circuits and methods for use in a sync separator. A comparator compares a video signal to a video reference voltage to produce a sliced sync signal that has a frequency that is equal to a scan frequency of a horizontal sync embedded in the video signal. A frequency-to-voltage converter converts the sliced sync signal to a voltage control signal having an amplitude that is inversely proportional to the scan period of the horizontal sync embedded the video signal. A voltage-to-timed interval converter that converts the voltage control signal to a timer signal that has timed intervals that are that are inversely proportional to the amplitude of the voltage control signal, and thus proportional to the scan period of the horizontal sync embedded in the video signal.

Abstract: Circuit methods, and apparatus that provide waveforms having controlled rise and fall times, as well as accurate peak voltages. One embodiment provides circuitry for generating a clock signal and a current that are adjusted for an on-chip capacitance variation. This current is then used to generate rising and falling edges of a waveform. The clock signal is used to determine timing of transitions in the waveform. A bandgap or similar reference voltage is used to determine the peak voltage. This waveform is then gained using an amplifier circuit, and the output of the amplifier circuit is used as a programming voltage waveform for an EE-PROM. One embodiment further uses non-overlapping clocks to drive a charge pump that is used to generate a supply voltage for the amplifier circuit that far exceeds the available on-chip supply voltages.

Abstract: The cleaning of particles from an electrostatic chuck. In one embodiment, a method of cleaning an electrostatic chuck in a processing chamber is disclosed. The method comprises directing a flow of gas across the electrostatic chuck to dislodge particles from the electrostatic chuck and removing the flow of gas and particles through an exhaust port in the processing chamber. In this embodiment, the vacuum integrity of the chamber is not compromised during the cleaning of the electrostatic chuck.

Abstract: An electroluminescent driver circuit with improved power consumption efficiency. In one embodiment, an electroluminescent driver circuit comprises a load to provide illumination, an inductor, a transistor and a plurality of switches. The inductor has a first side coupled to a positive terminal of a power supply and a second side selectively coupled to the load. The transistor is coupled to selectively conduct current from the second side of the inductor to a ground terminal of the power supply in response to a digital signal. The plurality of switches are coupled to the load to selectively charge and discharge the load. Moreover, the switches selectively provide a discharge path for positive charge on the load to be discharged to the positive terminal of the power supply.

Abstract: Embodiments of the present invention relate to systems and methods for providing flexible multipulse strategies. In specific embodiments, a plurality of multipulse location registers are dedicated to storing multipulse location information. Each of a plurality of different mark-lengths that can result in at least one multipulse is mapped to one or more bit location within the multipulse location registers, such that a unique multipulse execution strategy can be defined for each of the plurality of different mark-lengths. Each bit location within the multipulse location registers can contain a first type of bit or a second type of bit. The first type of bit is used to indicate where to execute a multipulse, and the second type of bit is used to indicate where to not execute a multipulse. This abstract is not intended to be a complete description of the various embodiments of the present invention.

Abstract: Methods and system are provided that enable unique write strategies to be selected without having to provide custom chips. Specific embodiments allow a user to specify which combinations, of total possible combinations, of space-to-mark lengths and mark-to-space lengths can have unique timing parameters defined in a portion of timing memory dedicated to storing space-to-mark and mark-to-space timing parameters, where unique timing parameters are defined for less than the total possible combinations of space-to-mark lengths and mark-to-space lengths. Embodiments also allow a user to select among different combination of timing mode and modulation code.

Abstract: To prevent a voltage glitch in the regulated DC output voltage of a PWM/PFM DC-DC converter when switching between PFM and PMW modes, the error amplifier of the converter's PWM regulation path is provided with a DC voltage offset correction mechanism. This mechanism “zeros-out” DC voltage offsets that may be present in the voltage regulation path, thereby enabling the error amplifier to accurately regulate the converter's output voltage. When the converter transitions between PFM and PWM modes, the DC offset correction mechanism establishes initial conditions of the error amplifier that effectively ensure that the converter's regulated output voltage at the beginning of a new “switched-to” PWM mode cycle is DC offset-free.

Abstract: A synthetic ripple generator that controls conversion of an input voltage to an output voltage while maintaining a relatively constant switching frequency including a ripple capacitor and resistor, a transconductance amplifier circuit, an output error circuit, a frequency control circuit and a hysteretic comparator. The ripple capacitor and resistor develop a ripple voltage. The transconductance amplifier circuit switches, based on a PWM signal, between charging the ripple capacitor based on the input voltage and discharging the ripple capacitor based on the output voltage. The output error circuit provides a compensation voltage indicative of an error of the output voltage. The frequency control circuit develops a ripple window voltage relative to the compensation voltage to adjust switching frequency.

Abstract: A battery charger controller is coupled to DC output terminals of an AC-DC (or DC-DC) adapter containing an AC-DC (or DC-DC) converter. A controlled current flow path between input and output terminals of the battery charger controller circuit is controlled to provide a substantially constant current to charge the battery to a nominal battery voltage. When a constant voltage output of the said adapter transitions to a value that limits available charging current to a value less than programmed constant charging current, current flow drive for the controlled current flow path is increased for a limited time interval. Thereafter, the controlled current flow path gradually reduces charging current as the battery voltage remains at its nominal battery voltage until the charge is complete or otherwise terminated.

Abstract: In order to minimize switching-induced electromagnetic interference in a power supply switching circuit of the type used to control the AC power for multiple high voltage devices, such as cold cathode fluorescent lamps employed for backlighting a large scale liquid crystal display, the gating signals that are used to switch lamp-driving inverter circuits ON and OFF are staggered, or slightly offset in time, so that no two switching devices will be switched at the same time. By slightly offset in time is meant that the time differential between any pair of switching signals is relatively small compared to the period of the switching signal frequency. This has the effect of spreading out and thereby diminishing the magnitude of the spectral content of both capacitively and inductively coupled transients that are produced at switching times of the inverter circuits.

Abstract: A multiphase DC-to-DC converter includes at least two phase circuits each having upper and lower power switches and a front-end inductor that is operative for forming a resonant tank circuit with the phase circuits to ensure zero voltage switching and minimizing power losses.

Abstract: A sliding-mode switching power supply (24) having N phases (28) and a method of operating the power supply (24) are provided. N switches (30) are coupled to a bipolar power source (22), with each switch (30) effecting one phase (28). An inductance (32) is coupled to each switch (30), and a capacitance (36) is coupled to the inductances (32). A load (26) is coupled across the capacitance (36). A monitor circuit (38) is coupled to the inductances (32) and the capacitance (36) and configured to monitor currents (IL) through the inductances (32) and/or a voltage (VC) across the capacitance (36). A sliding-surface generator (78) is coupled to the monitor circuit (38) and generates a single sliding surface (?) for all phases (28). A constant-frequency control (104) forms a variable window (??) for the sliding surface (?). A switching circuit (138) switches the switches (30) at a switching frequency (fS) determined by the variable window (??).

Abstract: A synthetic ripple regulator including a synthetic ripple voltage generator that generates a synthetic ripple voltage indicative of the ripple current through an output inductor. The regulator uses the synthetically generated ripple voltage to control toggling of a hysteretic comparator for developing the pulse width modulation (PWM) signal that controls switching of the regulator. In a non-limiting implementation, a transconductance amplifier monitors the phase node voltage of the inductor and supplies an inductor voltage-representative current to a ripple capacitor, which produces the synthetic ripple voltage. Using the replicated inductor current for ripple regulation results in low output ripple, input voltage feed forward, and simplified compensation.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: An apparatus and method for controlling the operation of a utility device, such as a cold cathode fluorescent lamp that is powered in accordance with a pulse width modulation (PWM) signal, includes an analog sensor which monitors the utility device to derive an output signal representative of the PWM signal. An integrating analog-to-digital converter (ADC), which is coupled to the sensor and has its operation synchronized with an integral multiple of the period of the PWM signal, produces an output representative of an average of the output of the utility device.

Abstract: A voltage regulator circuit arrangement limits the DC voltage applied to a tip and ring amplifiers of a subscriber line interface circuit (SLIC), each of which has a first polarity input coupled to a first current flow path to which a DC input (battery) voltage is coupled. A first current source supplies a first current derived via a low pass filter path from that flowing through the first current flow path to a second polarity input node of the tip amplifier, while a second current source supplies a similarly low pass filter path-derived second current to a second polarity input node of the ring amplifier. A voltage regulator is coupled with the first current flow path and is operative to regulate the voltage at the first polarity inputs of the tip and ring amplifiers to a regulated voltage value Vreg, so that the magnitudes of the first and second currents are based upon the regulated voltage value Vreg.