Abstract: A semi-clockless, cascaded, current-mode regulator has a first regulator that receives a clock signal from a controller. By ‘semi-clockless’ is meant that a clock signal is applied to the first of a cascaded plurality of regulators, and that as a result of the cascading of clock delay circuits in each of the regulators, the remaining regulators receive sequentially delayed versions of the clock signal applied to the first regulator. The regulators are coupled to control the operations of associated pulse width modulation controlled switching circuits. Outputs of the switching circuits are combined to realize a multi-phase output voltage.

Abstract: A monolithic 1.75 is mounted in a speaker cabinet 1.71 to drive the voice coil 1.74 of the speaker 1.70. The monolithic integrated circuit may be a class D amplifier 1.10, and is at least a half-bridge or full bridge power MOSFET device. Structures and process for forming the mos switching devices 2.20 of the bridge driver circuits are disclosed. Also disclosed is the N+ buried layer 4.14 of the QVDMOS transistors 4.43 of the bridge circuits.

Abstract: The present invention relates to an integrated circuit. The integrated circuit includes a substrate, at least one device region formed in the substrate, a patterned layer of oxide, a first and second layer of nitride and at least one metal contact region. The patterned layer of oxide is formed over a surface of the substrate, wherein the patterned layer provides at least one opening to the surface of the substrate adjacent the at least one device region. The first layer of nitride is formed over the patterned oxide layer. The second nitride layer is formed along sidewalls to the at least one opening. The patterned oxide layer is sealed with the first and second nitride layers. The at least one metal contact region is formed in the at least one opening.

Abstract: A bidirectional crosspoint switch interface employs a pair of backward-connected transimpedance amplifiers of the type disclosed in the U.S. Patent to L. Enriquez, U.S. Pat. No. 6,411,163, and associated scaling current mirrors that drive nodes of associated reverse signal cancellation circuits. The reverse signal cancellation circuits are coupled to respective pairs of ports of the crosspoint switch and input and output ports of 1:1 current mirrors, in a manner that affords bidirectional buffering between the crosspoint switch and a pair of bidirectional signaling ports that terminate respective signaling links, without signal reflections.

Abstract: Circuits and methods for damping out parasitic resonance within a packaged integrated circuit (IC) are provided. A conductive path including a resistor and a conductor is added in parallel with a conductive path that provides power to components within a die of the packaged IC. When implemented in a packaged laser driver integrated circuit (IC), a conductive path including a resistor and a conductor in placed in parallel with a conductive path that provides a laser driver output, of the packaged laser driver IC, to a laser diode. This abstract is not intended to be a complete description of the various embodiments of the present invention.

Abstract: Amplifier circuits that generate CM currents are provided. Amplifier circuits that generator DM currents are also provided. Fully differential current feedback amplifier circuits with separate CM and DM inputs are also provided. Such amplifier circuits combine the benefits of CFA designs, such as high slew rate and bandwidth, with independent control of DM and CM signals. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A method of forming efficient photodiodes includes the steps of providing a substrate having a p-surface region on at least a portion thereof, implanting a shallow n-type surface layer into the surface region, and forming a multilayer first anti-reflective (AR) coating on the n-type surface layer. The surface layer is preferably an As or Sb surface layer. The forming the AR step include the steps of depositing or forming a thin oxide layer having a thickness of between 1.5 nm and 8 nm on the shallow surface layer, and depositing a second dielectric different from the thin oxide layer on the thin oxide layer, such as a silicon nitride layer.

Abstract: A floating gate voltage level shift circuit is disclosed for generating a voltage reference which can operate on a low supply voltage Vcc by providing a circuit that enables the floating gate to be set accurately to a positive voltage during a SET operation and subsequently shifted down to a lower voltage for a READ operation. The floating gate voltage level shift circuit comprises a differential amplifier with two floating gates, a first floating gate and a second floating gate where the second floating gate is capacitively coupled to either a READ voltage or a Vshift voltage. The floating gate voltage level shift circuit operates in two primary modes, a SET operation and a READ operation. During the SET operation, the C1p capacitor of the second floating gate is connected to a Vshift voltage, rather than ground, while accurately setting the floating gate a positive voltage.

Abstract: A transmitter for a digital transmission signal includes a pre-distorter to improve linearity of a power amplifier. An amplified transmission signal is conditioned into a narrowband feedback signal that is responsive to a logarithm of the power appearing in out-of-band components of the amplified transmission signal. The feedback signal is processed in a pre-distortion processor that implements a genetic algorithm to adapt pre-distortion functions implemented in the pre-distorter and improve linearity over time. The genetic algorithm tests a population of randomly-generated pre-distortion functions for fitness. A baseline component of the coefficients from pre-distortion functions used in a subsequent population tracks the best-fit pre-distortion function from the current population, allowing the use of a limited search space. New populations are generated from old populations using an elitism process, and randomized crossover, and mutation processes.

Abstract: A regulator supplies a regulated voltage to an electronic component with a plurality of phases with varying response rates. The regulator includes an output node that provides a regulated supply voltage, a first main-phase drive circuit that provides a first main load current to the output node and that has an on time and an off time, and a first transient-phase drive circuit that has a first transient load current to the output node that has an on time and an off time that are respectively less than the on and off times of the first main-phase drive circuit.

Abstract: A method of a modeling metallization parasitics with the use of a simulation program. In one embodiment, a method of simulating interconnect lines in an electronic design automation simulation is disclosed. The method comprises partitioning the interconnect lines into groups of interconnect lines. Each group of interconnect lines does not have interactions with any of the other groups of interconnect lines. Moreover, at least one of the groups of interconnect lines contains at least three interconnect lines. The interconnect lines in each group are modeled. The modeling includes at least one of modeling mutual inductances and modeling of mutual capacitances.

Abstract: An inductor current measurement scheme generates an output voltage as a function of inductor current in a pulse width modulation-based DC—DC voltage converter. The converter has an upper controlled switch and a lower controlled switch coupled in series between an input voltage terminal and a reference voltage terminal. A common connection of the upper controlled switch and the lower controlled switch provides a phase node voltage. An inductor L and a parasitic direct current resistance (DCR) are coupled between the phase node and an output node coupled to a load. The scheme generates a sense current as a function of the difference between the phase node voltage and the output voltage. This sense current is then supplied to a resistor-capacitor network comprised of a resistor Rs and a capacitor Cs, wherein the product of Rs*Cs=L/DCR, so as to produce a voltage across the resistor-capacitor network that is proportional to the inductor current.

Abstract: A method of forming bipolar transistors by using the same mask to form the collector region in a substrate of an opposite conductivity type as to form the base in the collector region. More specifically, impurities of a first conductivity type are introduced into a region of a substrate of a second conductivity type through a first aperture in a first mask to form a collector region. Impurities of the second conductivity type are introduced in the collector through the first aperture in the first mask to form the base region. Impurities of the first conductivity type are then introduced into the base region through a second aperture in a second mask to form the emitter region. The minimum dimension of the first aperture of the first mask is selected for a desired collector to base breakdown voltage. This allows tuning of the breakdown voltage.

Abstract: A voltage-coupling and loop current supply mechanism controllably turns on an output transistor within the tip amplifier circuitry portion of the speech amplifier to controllably apply a prescribed voltage to the telephone line during on-hook/standby mode. This controllably applied voltage serves as a source of loop current when the phone goes off-hook. The ring lead portion of the tip/ring wireline pair is connected to a controlled current sink, which is coupled to the output of a voltage regulator referenced to the battery voltage. This controlled current sink is used to sink a prescribed loop current from the tip/ring pair when the phone goes off-hook. When the phone goes off-hook and loop current is detected, the voltage-supply mechanism provided by the tip amplifier's output transistor is terminated, and the speech amplifier is placed in its normal speech amplifier mode.

Abstract: A rail—rail current sense amplifier including a low voltage current sense amplifier circuit, a high voltage current sense amplifier circuit, a first resistive device, and a selection circuit. The current sense amplifier senses current through a current sense device coupled to a battery node. The low voltage current sense amplifier circuit develops a first current that is proportional to current through the current sense device for low voltages up to an upper voltage threshold. The high voltage current sense amplifier circuit develops a second current that is proportional to current through the current sense device for high voltages down to a lower voltage threshold. The selection circuit selectively applies the first current to the first resistive device for low voltages up to the upper voltage threshold, and selectively applies the second current to the first resistive device for high voltages down to the lower voltage threshold.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each sample-and-hold circuit in a first group of N sample-and-hold (S/H) circuits is connected to a corresponding output of the analog demultiplexer. Similarly, each S/H circuit in a second group of N S/H circuits is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the S/H circuits in the first group and a second input connected to an output of a corresponding one of the S/H circuits in the second group.

Abstract: A multi-reference voltage generator includes an interface controller, a first bank of N m-bit registers and a second bank of N m-bit registers. A first multiplexer has inputs connected to outputs of the first and second bank of registers. An m-bit digital-to-analog (DAC) has an m-bit parallel input connected to an output of the first multiplexer. An analog demultiplexer has an input connected to an analog output of the m-bit DAC. Each voltage storage device in a first group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. Similarly, each voltage storage device in a second group of N voltage storage devices is connected to a corresponding output of the analog demultiplexer. N further multiplexers each have a first input connected to an output of a corresponding one of the voltage storage devices in the first group and a second input connected to an output of a corresponding one of the voltage storage devices in the second group.

Abstract: A method of forming a non-single-crystalline capacitor in an integrated circuit. It includes the steps of forming a first non-single-crystalline layer on a gate dielectric layer of a substrate of an integrated circuit. Next, a capacitor dielectric layer is formed on the first non-single-crystalline layer, and a second non-single-crystalline layer is formed on the capacitor dielectric layer. Portions of the second non-single-crystalline layer are removed to define a top plate of the capacitor. Portions of the capacitor dielectric layer are removed to define a dielectric of the capacitor. Also, portions of the first non-single-crystalline layer are removed to define the bottom plate of the capacitor.

Abstract: The cleaning of particles from an electrostatic chuck. In one embodiment, a method of cleaning an electrostatic chuck in a processing chamber is disclosed. The method comprises directing a flow of gas across the electrostatic chuck to dislodge particles from the electrostatic chuck and removing the flow of gas and particles through an exhaust port in the processing chamber. In this embodiment, the vacuum integrity of the chamber is not compromised during the cleaning of the electrostatic chuck.

Abstract: A sliding-mode switching power supply (24) having N phases (28) and a method of operating the power supply (24) are provided. N switches (30) are coupled to a bipolar power source (22), with each switch (30) effecting one phase (28). An inductance (32) is coupled to each switch (30), and a capacitance (36) is coupled to the inductances (32). A load (26) is coupled across the capacitance (36). A monitor circuit (38) is coupled to the inductances (32) and the capacitance (36) and configured to monitor currents (IL) through the inductances (32) and/or a voltage (VC) across the capacitance (36). A sliding-surface generator (78) is coupled to the monitor circuit (38) and generates a single sliding surface (?) for all phases (28). A constant-frequency control (104) forms a variable window (??) for the sliding surface (?). A switching circuit (138) switches the switches (30) at a switching frequency (fS) determined by the variable window (??).