Abstract: A method and device for determining, in a non-destructive way, at least the active carrier profile from an unknown semiconductor substrate are disclosed. In one aspect, the method comprises generating 2m independent measurement values from the m reflected signals and correlating these 2m measurement values with 2m independent carrier profile values. The method further comprises generating additional 2m measurement values to allow determining the active carrier profile and a second parameter profile by correlating the 4m measurement values with the 4m profile values. The method further comprises generating a total of 2m[n.k] measurement values to allow determining [n.k] independent material parameter depth profiles, each material parameter profile having m points.

Abstract: A device and a method for bonding elements are described. A first solder ball is produced on a main surface of a first element. A second solder ball is produced on a main surface of a second element. Contact is provided between the first solder ball and the second solder ball. The first and second elements are bonded by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a first layer of non-conductive material and the second solder ball is laterally embedded in a second layer of non-conductive material, such that the upper part of the first solder ball and upper part of the second solder ball are not covered by the non-conductive material. A third solder volume is applied on one or both of the embedded first or second solder balls, prior to the bonding.

Abstract: A method of designing a lithographic mask for use in lithographic processing of a substrate is disclosed. The lithographic processing comprises irradiating mask features of a lithographic mask using a predetermined irradiation configuration. In one aspect, the method comprises obtaining an initial design for the lithographic mask comprising a plurality of initial design features having an initial position. The method further comprises applying at least one shift to at least one initial design feature and deriving there from an altered design so as to compensate for shadowing effects when irradiating the substrate using a lithographic mask corresponding to the altered design in the predetermined irradiation configuration. Also disclosed herein are a corresponding design, a method of setting up lithographic processing, a system for designing a lithographic mask, a lithographic mask, and a method of manufacturing it.

Abstract: A tunnel field effect transistor (TFET) is disclosed. In one aspect, the transistor comprises a gate that does not align with a drain, and only overlap with the source extending at least up to the interface of the source-channel region and optionally overlaps with part of the channel. Due to the shorter gate, the total gate capacitance is reduced, which is directly reflected in an improved switching speed of the device. In addition to the advantage of an improved switching speed, the transistor also has a processing advantage (no alignment of the gate with the drain is necessary), as well as a performance improvement (the ambipolar behavior of the TFET is reduced).

Abstract: A system and method for motion detection and the use thereof in video coding are disclosed. In one aspect, a method of defining a region of motion within a video frame in a sequence of video frames comprises loading a current video frame and at least one reference video frame from the sequence, the reference video frame being different from the current video frame. The method further comprises applying filtering operations on the current and the reference video frame in order to obtain at least two scales of representation of the current and the reference video frame. The method further comprises determining for each of the scale representations a video-frame like representation of the structural changes between the current and the reference video frame. The method further comprises combining the video-frame like representations of different scales. The method further comprises determining one or more regions of motion from the combination.

Abstract: The present invention relates to a method for obtaining monocrystalline or single crystal nanowires. Said nanowires are grown in a pattern making use of electro-chemical deposition techniques. Most preferred, the electrolytic bath is based on chlorides and has an acidic pH. Single element as well as combinations of two elements nanowires can be grown. Depending on the element properties the obtained nanowire can have metallic (conductive) or semi-metallic (semi-conductive) properties. The observed nanowire growth presents an unusual behavior compared to the classical nanowire template-assisted growth where a cap is formed as soon as the metal grows out of the pattern. Under given conditions of bath composition and potential (current) settings the nanowires grow out of the pattern up to a few microns without any significant lateral overgrowth.

Abstract: Disclosed herein are memory devices comprising a plurality of memory cells to which a standby voltage is to be supplied during standby mode to avoid loss of data, and methods of operating said memory devices, the methods comprising: (a) determining an actual value of a bit integrity parameter of the memory cells; (b) comparing said actual value with a predetermined minimal value of the bit integrity parameter which takes into account possible variations in cell properties as a result of process variations; and (c) adjusting the standby voltage towards a more optimal value based on the result of the comparison in such a way that said bit integrity parameter determined for said more optimal value of the standby voltage approaches the predetermined minimal value. The circuitry for measuring the bit integrity parameter preferably comprises a plurality of replica test cells which are added to the memory matrix.

Abstract: The invention relates to a method for cleaning semiconductor surfaces to achieve to removal of all kinds of contamination (particulate, metallic and organic) in one cleaning step. The method employs a cleaning solution for treating semiconductor surfaces which is stable and provokes less or no metal precipitation on the semiconductor surface.

Abstract: The invention provides a single-step method for removing bulk metal contamination from III-V semiconductor substrates. The method comprises immersing a metal contaminated III-V semiconductor substrate in a mixture of sulfuric acid and peroxide with a volume ratio of sulfuric acid to peroxide (e.g., hydrogen peroxide) between about 3:1 and about 9:1. After treating the III-V semiconductor substrates with the sulfuric acid-peroxide mixture, the bulk metal contamination may be substantially removed from the substrate while a surface roughness of the substrate after treatment of below about 0.5 nm RMS (2 ?m×2 ?m) is obtained. The invention further provides a method for manufacturing a semiconductor device by removing bulk metal contamination according to the single-step method of the invention before performing processing steps for forming the semiconductor device.

Abstract: A method is disclosed for lithographic processing. In one aspect, the method comprises obtaining a resist material with predetermined resist properties. The method further comprises using the resist material for providing a resist layer on the device to be lithographic processed. The method further comprises illuminating the resist layer according to a predetermined pattern to be obtained. The obtained resist material comprises a tuned photo-acid generator component and/or a tuned quencher component and/or a tuned acid mobility as to reduce watermark defects on the lithographic processed device. In another aspect, a corresponding resist material, a set of resist materials, use of such materials and a method for setting up a lithographic process are disclosed.

Abstract: The present invention relates generally to a method and device of partial or complete functional restoration of the damaged nervous system by bridging a cavity in the central or peripheral nervous tissue and, more particularly to a system and method for repairing the nerve signal transduction by bridging of the cavity with microelectrode elements more particular microelectrodes for stimulation and microelectrodes for recording.

Abstract: Methods for the quantification of hydrophilic properties of a porous material, as well as determining a depth of damage of a porous material are disclosed. An example method includes performing a first ellipsometric measurement on the porous material using a first adsorptive having a first wetting angle. The example method further includes performing a second ellipsometric measurement on the porous material using a second adsorptive having a second wetting angle, wherein the first and second wetting angles are different towards the porous material. The hydrophilic properties of the porous material are determined based, at least in part, on the first and second ellipsometric measurements.

Abstract: The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region.

Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.

Abstract: The present disclosure relates to methods and solutions for growing metal charge-transfer salts on a metal surface, such as a metal layer at the bottom of a via hole. The method makes use of a solution comprising a salt additive. The temperature during growth is in the range of ?100° C. to +100° C. The method allows controlled growth of the metal charge transfer salt inside via hole while limiting growth outside the via hole. The method further limits corrosion of the metallic connections at the bottom of the via hole.

Abstract: An electrostatic discharge (ESD) protection circuit for the protection of an electronic circuit from an ESD event. The electronic circuit, in operation, is provided with a supply voltage and a reference voltage (typically electrical ground) via voltage terminals and/or power supply buses. The protection circuit includes two bipolar transistors in series, where the transistors are coupled between the supply voltage terminal/bus and the reference voltage terminal/bus. The bases of the transistors are coupled via a connection including two resistors in series, where the connection point between the two resistors is coupled with the connection point between the two transistors.

Abstract: A semiconductor device is disclosed. In one aspect, the device comprises a channel area, the channel area comprising a channel layer in which charge carriers can move when the transistor is turned on, in order to pass a current through the transistor. The device further comprises a source area and a drain area contacting the channel layer for providing current to and from the channel layer. The method further comprises a gate electrode, preferably provided with a gate dielectric between the gate electrode and the channel layer. The channel layer may comprise a III-V material, and the source and drain areas comprise SiGe, being SixGe1-x, with x between 0 and 100%, arranged so that heterojunctions are present between III-V material and SiGe, wherein the heterojunctions are oriented so as to intersect with the gate dielectric or the gate electrode.

Abstract: The present invention provides an impurity measuring method comprising the steps of dropping a drop of a first solution on the surface of a substrate to be measured, moving the drop dropped on the surface of the substrate so that the drop is kept in contact with the surface and collects an impurity absorbed on the surface, recovering the drop after the movement and analyzing the recovered drop by chemical analysis to determine the type and concentration of the impurity, characterized in that the first solution is phobic to the substrate and the substrate consists substantially of Ge. The method is of particular importance for measuring metallic contamination on the surface of Ge substrates.

Abstract: A method for forming deep trench or via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), depositing spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming an airgap is demonstrated successfully for use as deep trench isolation structures in BiCMOS devices.

Abstract: A new, effective and cost-efficient method of introducing Fluorine into Hf-based dielectric gate stacks of planar or multi-gate devices (MuGFET), resulting in a significant improvement in both Negative and Positive Bias Temperature Instabilities (NBTI and PBTI) is provided. The new method uses an SF6 based metal gate etch chemistry for the introduction of Fluorine, which after a thermal budget within the standard process flow, results in excellent F passivation of the interfaces. A key advantage of the method is that it uses the metal gate etch for F introduction, requiring no extra implantations or treatments. In addition to the significant BTI improvement with the novel method, a better Vth control and increased drive current on MuGFET devices is achieved.