Patents Assigned to InterUniversitaire Microelektronica
  • Publication number: 20080096372
    Abstract: A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Marc Demand, Denis Shamiryan, Vasile Paraschiv
  • Publication number: 20080096383
    Abstract: A method of manufacturing a semiconductor device with at least a first dielectric material and a second dielectric material is disclosed. In one aspect, the method comprises providing a first dielectric material on a substrate. The method further comprises providing a patterned sacrificial layer covering the first dielectric material in at least a first region of the substrate. The method further comprises providing a second dielectric material covering the patterned sacrificial layer in the first region and covering the first dielectric material in at least a second region, the second region being different from the first region. The method further comprises patterning the second dielectric material such that the patterned second dielectric material covers the first dielectric material in the second region but not the patterned sacrificial layer in the first region. The method further comprises removing the patterned sacrificial material.
    Type: Application
    Filed: October 18, 2007
    Publication date: April 24, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventors: Howard Tigelaar, Stefan Kubicek, HongYu Yu
  • Publication number: 20080098270
    Abstract: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.
    Type: Application
    Filed: May 11, 2005
    Publication date: April 24, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventor: Ward De Ceuninck
  • Publication number: 20080096374
    Abstract: A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO3) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device. The selective removal and etch of this high-k material is very difficult since Dy and Sc (and their oxides) are difficult to etch. The etching could however be easily stopped on them. For patterning of the metal gates comprising TiN and TaN on top of rare earth based high-k layer a chlorine-containing gases (Cl2 and BCl3) can be used since titanium ant tantalum chlorides are volatile and reasonable selectivity to other material present on the wafer (Si, SiO2) can be obtained. The Dy and Sc chlorides are not volatile, but they are water soluble.
    Type: Application
    Filed: October 22, 2007
    Publication date: April 24, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Denis Shamiryan, Marc Demand, Vasile Paraschiv
  • Patent number: 7361453
    Abstract: A method of manufacturing a semiconductor device with precision patterning is disclosed. A structure of a small dimension is created in a material, such as a semiconductor material, using a first and a second pattern, the patterns being identical but displaced over a distance with respect to each other. Two mask layers are used, wherein the first pattern is etched into the upper mask layer with a selective etch, and the second pattern is created on the upper mask layer or on the lower mask layer at locations where the upper mask layer has been removed. A part of the lower mask layer and/or the upper mask layer is etched according to the second pattern, resulting in a mask formed by remaining parts of the lower and upper mask layers, the mask having a structure with a dimension determined by a displacement of the second pattern with respect to the first pattern.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: April 22, 2008
    Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC), Koninklijke Philips Electronics
    Inventors: Greja Johanna Adriana Maria Verheijden, Pascal Henri Leon Bancken, Johannes van Wingerden
  • Publication number: 20080085480
    Abstract: A method for removing a resist layer from a substrate is described. The method for removing a resist layer from a substrate, wherein the resist layer comprises bulk resist contacting the substrate and a resist crust being present at the outer surface of the resist layer, includes providing at least locally a liquid organic solvent on the resist layer contacting the substrate, for which the bulk resist is soluble in the organic solvent and the resist crust is substantially insoluble in the organic solvent. The method further includes stripping the resist layer from the substrate by providing megasonic energy to the organic solvent, creating organic solvent cavitations for fracturing the resist crust, and dissolving the bulk resist in the organic solvent.
    Type: Application
    Filed: September 20, 2007
    Publication date: April 10, 2008
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Guy Vereecke, Quoc Toan Le, Els Kesters
  • Patent number: 7347557
    Abstract: A projection system comprising a light source is disclosed, wherein the light source comprises at least two light emitters arranged to be optically positionable alternately in a first position and a second position by an optical positioning means wherein said optical positioning means is arranged to change the light emission from said light emitters to a preferred optical path being said first position, a power source arranged to empower said light emitters, wherein the light emitter optically positioned in said first position is empowered by said power source and the light emitter optically positioned in said second position is not empowered.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: March 25, 2008
    Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC), Universiteit Gent
    Inventor: Herbert De Smet
  • Publication number: 20080067495
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents a nanowire-based TFET with a germanium (Ge) tunnel barrier in an otherwise silicon (Si) channel is used. A nanowire is introduced such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations. Multiple layers of logic can therefore be envisioned with these nanowire Si/Ge TFETs resulting in ultra-high on-chip transistor densities.
    Type: Application
    Filed: June 20, 2007
    Publication date: March 20, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventor: Anne S. Verhulst
  • Publication number: 20080067607
    Abstract: Tunnel field-effect transistors (TFETs) are regarded as successors of metal-oxide semiconductor field-effect transistors (MOSFETs), but silicon-based TFETs typically suffer from low on-currents, a drawback related to the large resistance of the tunnel barrier. To achieve higher on-currents an elongate monocrystalline nanostructure-based TFET with a heterostructure made of a different semiconducting material (e.g. germanium (Ge)) is used. An elongate monocrystalline nanostructure made of a different semiconducting material is introduced which acts as source (or alternatively drain) region of the TFET. The introduction of the heterosection is such that the lattice mismatch between silicon and germanium does not result in a highly defective interface. A dynamic power reduction as well as a static power reduction can result, compared to conventional MOSFET configurations.
    Type: Application
    Filed: September 14, 2007
    Publication date: March 20, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Katholieke Universiteit Leuven K.U.LEUVEN R&D
    Inventors: Anne S. Verhulst, William G. Vandenberghe
  • Publication number: 20080055815
    Abstract: One inventive aspect relates a variable capacitor comprising first and second electrically conductive electrodes, arranged above a support structure and spaced apart from each other and defining the capacitance of the capacitor. At least one of the electrodes comprises at least one bendable portion. The bendable portion(s) are actuated by a DC voltage difference which is applied over the electrodes to vary the capacitance. In preferred embodiments, the support structure comprises a layer of higher permittivity than the atmosphere surrounding the electrodes and the electrodes configure as an interdigitated structure upon actuation. Also disclosed is a 2-mask process for producing such capacitors.
    Type: Application
    Filed: August 17, 2007
    Publication date: March 6, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventor: Xavier Rottenberg
  • Publication number: 20080057683
    Abstract: Devices and methods for junction formation in manufacturing a semiconductor device are disclosed. The devices have shallow junction depths far removed from end-of range defects. The method comprises forming an amorphous region in a crystalline semiconductor such as silicon down to a first depth, followed by implantation of a substitutional element such as carbon to a smaller depth than the first depth. The region is then doped with suitable dopants, e.g. phosphorus or boron, and the amorphous layer recrystallized by a thermal process.
    Type: Application
    Filed: August 3, 2007
    Publication date: March 6, 2008
    Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), KONINKLIJKE PHILIPS ELECTROONICS
    Inventor: Bartlomiej Pawlak
  • Publication number: 20080057685
    Abstract: A method for forming doped metal-semiconductor compound regions in a substrate is disclosed. In one aspect, a method for forming silicide regions in a substrate comprises partially regrowing an upper amorphous region on top of a crystalline part of the substrate, after having doped the upper amorphous region, to form a regrown region, thereby leaving a remaining upper amorphous region in between the regrown region and the major surface of the substrate. The remaining upper amorphous region is used for forming the metal-semiconductor compound.
    Type: Application
    Filed: July 30, 2007
    Publication date: March 6, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC) vzw, Koninklijke Philips Electronics
    Inventors: Bartlomiej Pawlak, Anne Lauwers
  • Patent number: 7338896
    Abstract: A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: March 4, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Serge Vanhaelemeersch, Eddy Kunnen, Laure Elisa Carbonell
  • Publication number: 20080050897
    Abstract: A method for doping a multi-gate device is disclosed. In one aspect, the method comprises patterning a fin in a substrate, depositing a gate stack, and doping the fin. The process of doping the fin is done by depositing a blocking mask material at least on the top surface of the fin after the patterning of the gate stack. After the deposition of the blocking mask material dopant ions are implanted whereby the blocking mask material partially or completely blocks the top surface of the fin from these dopant ions.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC) vzw
    Inventor: Anil Kottantharayil
  • Publication number: 20080050919
    Abstract: A method for patterning high aspect ratio vias is provided. More specifically a dry etching method is provided for patterning deep vias or vias with high aspects ratios thereby eliminating the hard mask undercut. A method is provided to create (pattern) deep vias in a substrate for use in three dimensional stacked semiconductor devices and/or structures. More specifically, a method is provided for patterning deep vias with an aspect ratio up to 10 into a Si substrate with smooth via sidewalls and sufficient slope to enable metallization.
    Type: Application
    Filed: July 24, 2007
    Publication date: February 28, 2008
    Applicant: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Joke Van Aelst, Herbert Struyf, Serge Vanhaelemeersch
  • Publication number: 20080048273
    Abstract: A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle ? different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 28, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC) vzw, STMicroelectronics (Croelles2) SAS
    Inventor: Damien Lenoble
  • Patent number: 7336931
    Abstract: An electrical device comprises analog conversion circuitry having an input and an output. The electrical device is essentially provided for converting a first input signal within a first frequency range applied to the input to a first output signal within a second frequency range different from the first frequency range at the output. The electrical device further comprises a signal adding means for adding at least a portion of the first output signal as second input signal to the first input signal. The analog conversion circuitry is also capable of converting the second input signal, which is within the second frequency range, back to the first frequency range. Additionally, a characteristic deriving means is provided for deriving at least one characteristic of the electrical device from the frequency converted second input signal, which appears at the output of the analog conversion circuitry.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: February 26, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventor: Jan Craninckx
  • Publication number: 20080046080
    Abstract: A packaged microelectronic device (20) is provided comprising at least one electrode (10) comprising a chip (18) embedded in a package. The chip (18) comprises a back electrode (17) located at a first side of the chip (18), and electronic circuitry (14) located at a second side of the chip (18), the second side being opposite to the first side, and wherein the back electrode (17) is part of the package. A method for forming such packaged microelectronic devices (20) is also described.
    Type: Application
    Filed: July 9, 2007
    Publication date: February 21, 2008
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Mathieu Vanden Bulcke, Eric Beyne
  • Publication number: 20080045684
    Abstract: A technique is described for the preparation of polymers according to a new process, in which the starting compound of formula (I) is polymerized in the presence of a base, in an organic solvent. The precursor polymer such obtained comprises structural units of the formula (II). In a next step, the precursor polymer (II) is subjected to a conversion reaction by thermal treatment. The arylene or heteroarylene polymer comprises structural units of the formula III. In this new process the dithiocarbamate group acts as a leaving group and permits the formation of a precursor polymer of structural formula (II), which has an average molecular weight from 5.000 to 500.000 Dalton and is soluble in common organic solvents. The precursor polymer with structural units of formula (II) is thermally converted to the conjugated polymer with structural formula (III).
    Type: Application
    Filed: July 18, 2007
    Publication date: February 21, 2008
    Applicants: Interuniversitair Microelektronica Centrum (IMEC), Limburgs Universitair Centrum
    Inventors: Dirk Vanderzande, Laurence Lutsen, Anja Henckens, Kristof Colladet
  • Patent number: 7332768
    Abstract: Non-volatile memory devices are disclosed. In a first example non-volatile memory device, programming and erasing of the memory device is performed through the same insulating barrier without the use of a complex symmetrical structure. In the example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to a charge storage region. Further in the example device, erasing is accomplished by tunneling positive carriers from the charge supply region to the charge storage region. In a second example non-volatile memory device, a charge storage region with spatially distributed charge storage region is included. Such a charge storage region may be implemented in the first example memory device or may be implemented in other memory devices. In the second example device, programming is accomplished by tunneling negative charge carriers from a charge supply region to the charge storage region.
    Type: Grant
    Filed: March 2, 2006
    Date of Patent: February 19, 2008
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Bogdan Govoreanu, Maarten Rosmeulen, Pieter Blomme