Abstract: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide.

Abstract: The present invention is related to a front-end circuit for an optical communication system including a laser module arranged for transmitting bursts of data signals over an optical network and a driving circuit for providing the bursts of data signals to the laser module. The front-end circuit further includes receiver means in connection with said laser module and arranged for receiving from the optical network optical echo signals. The laser module includes a laser diode arranged for transmitting the bursts of data signals. The driving circuit is arranged for setting a disabling signal for stopping the laser diode from transmitting bursts of the data signals. Fiber-related information can be extracted from the echo signals, such as distance-resolved optical fiber reflections and fiber attenuation.

Abstract: A method and apparatus for immersion lithography is described. The method includes positioning a semiconductor substrate under an optical immersion head assembly, providing an immersion liquid between the substrate and the optical immersion head assembly, and supplying a tensio-active gaseous substance along the perimeter of the contact area of the immersion liquid and the substrate. The immersion liquid contacts at least an area of the substrate. The tensio-active gaseous substance is chosen such that, when at least partially mixed with the immersion liquid, the mixture has a lower surface tension than the immersion liquid, thereby creating a surface tension gradient pulling the immersion liquid from the perimeter towards an inside portion of the contact area.

Abstract: A method for determining a concentration of an analyte is provided.

Abstract: A metal nanostructure is described. Such a metal nanostructure may comprise a nanometric metal core comprising gold, silver or an assembly or alloy of gold and silver, and one or more molecules attached to one or more surfaces of the nanometric metal core, where each of the molecules has the structural formula W-X-Y-Z, where W is an atom or a chemical group bound to the nanometric metal core, X is a hydrophobic spacer, Y is a hydrophilic spacer and Z is either hydrogen or a reactive group able to bind a reactive substrate or biomolecule. Such a metal nanostructure may be useful in making pharmaceutical compositions.

Abstract: The present invention is related to a method for controlled transport of magnetic beads between a position X and different position Y, such that the magnetic beads are manipulated or transported by applying successively a series of N local magnetic fields which have magnetic field gradients different from 0 in the neighborhood of said magnetic beads. Each of these N local magnetic fields is generated by a single current carrying structure, in which the current density is not constant. The invention generally relates to application in the domain of biochips and micro-arrays, used in diagnostics, genetics and molecular studies.

Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.

Abstract: A method of bonding two elements such as wafers used in microelectronics applications is disclosed. One inventive aspect relates to a method for bonding comprising producing on a first main surface of a first element a first solder ball, producing on a first main surface of a second element a second solder ball, providing contact between the first solder ball and the second solder ball, bonding the first element and the second element by applying a reflow act whereby the solder balls melt and form a joined solder ball structure. Prior to the bonding, the first solder ball is laterally embedded in a nonconductive material, such that the upper part of the first solder ball is not covered by the non-conductive material. Devices related to such methods are also disclosed.

Abstract: A multiple gate semiconductor device. The device includes at least two gates. The dopant distribution in the semiconductor body of the device varies from a low value near the surface of the body towards a higher value inside the body of the device.

Abstract: One embodiment includes a method for operating a terminal having at least one resource. The terminal is configured to execute at least one application in real-time. The execution of the application requires execution of at least two tasks. The method comprises selecting operating points for each of the tasks from a predetermined set without knowing all implementation details. The method further comprises determining at least one implementation parameter for the selected quality-resource utilization operating point, wherein the determining is performed for each of the tasks, and wherein the determined implementation parameter is different than the quality and resource utilization, and executing the tasks with their determined implementation parameter.

Abstract: A method is described for providing a predetermined optical path in an optical module, the predetermined optical path being defined by predetermined optical characteristics for the optical module. a modifiable optical element is provided at a predetermined position in the optical module, thus generating an initial optical path of the optical module. The modifiable optical element comprising at least one optical interface in the initial optical path. An optical signal is detected from a radiation beam on the initial optical path of the optical module. The optical interface of the modifiable optical element is then physically modified to generate at least one modified optical interface of the modifiable optical element. The physical modification takes into account the detected optical signal so as to obtain substantially the predetermined optical characteristics for the optical module.

Abstract: Micro electromechanical devices and methods for designing such devices are disclosed. An example micro electromechanical device includes at least two anchors. The example device also includes a floating element. The floating element extends between the at least two anchors and includes a predetermined reference portion. In at least one predetermined state during operation of the device, the reference portion is located within a predetermined reference plane. The floating element includes at least two flexible sections, where the at least two flexible sections each extends between the reference portion and a respective one of the anchors. In the example device, at least two of the at least two flexible sections include respective stress relieving elements. The stress relieving elements enable deflection of the floating element as a result of a stress gradient.

Abstract: A method of etching a semiconductor substrate is described, the method comprising the steps of applying a paste containing an etchant to the substrate, and carrying out a thermal processing step to etch a part or a layer of the substrate where the paste has been applied. The etchant paste is preferably a caustic etching paste. The etchant paste may be applied selectively to a major surface of the substrate to form a pattern of applied paste. For example, the paste may be applied by a printing method, such as screen-printing. The method may be used to produce solar cells.

Abstract: A method for producing narrow trenches in semiconductor devices. The narrow trenches are formed by chemically changing the properties of a first dielectric layer locally, such that the side walls of a patterned hole in the first dielectric layer is converted locally and becomes etchable by a first etching substance. Subsequently a second dielectric material is deposited in the patterned structure and the damaged part of the first dielectric material is removed such that small trenches are obtained.

Abstract: A method is described for setting up the lithographic processing of a substrate. The lithographic processing typically is characterized by a set of selectable process parameters, such as the thickness, real refractive index, and absorption coefficient of a bottom anti-reflective layer. The method includes selecting a set of values for the selectable process parameters, determining the substrate reflectivity in the resist layer for these parameters, and evaluating if the determined substrate reflectivity is smaller than a maximum allowable substrate reflectivity in the resist layer. The maximum allowable substrate reflectivity is determined according to a floating criterion, i.e., the maximum allowable substrate reflectivity depends on a Normalized Image Log Slope related parameter.

Abstract: A method for designing an ESD protected analog circuit is described. The method includes creating an analog circuit design comprising a plurality of interconnected functional components and circuit-level ESD protection components with predetermined electric properties for achieving a predetermined analog performance during normal operation of the circuit as well as a predetermined ESD robustness during an ESD event on the circuit. At least one ESD event is simulated on the analog circuit design to identify at least one weak spot in the circuit. Component-level ESD protection components are added into the analog circuit design around each identified weak spot to reduce failure of the weak spot during an ESD event.

Abstract: One embodiment of the invention relates to a method for fabricating a semiconductor device having a semiconductor structure with a silicon region which forms at least one connection region in and/or on a surface of a substrate. The method comprises forming a metal cluster layer from a first, non-siliciding metal, followed by the deposition of a metal layer consisting of a second, siliciding metal. A subsequent heat treatment is responsible for forming a metal silicide from the second metal, the atoms of the first metal being displaced in a direction substantially perpendicular to the surface of the substrate. According to one embodiment of the invention, the atoms of the first metal are displaced by the Kirkendall effect to beneath the metal silicide. If an MOST, for example, is being fabricated, this has advantages both at the location of the source and drain region and at the location of the gate electrode.

Abstract: The present invention is related to the realization of a simplified bottom electrode stack for ferroelectric memory cells. More particularly, the invention is related to ferroelectric memory cells wherein the ferroelectric capacitor is positioned directly on top of a contact plug. The bottom electrode stack is prepared by depositing a ferroelectric film atop an Ir or Ru metal electrode layer, then annealing the ferroelectric layer in an oxygen ambient wherein the partial pressure of oxygen is controlled at a level sufficient to oxidize the ferroelectric layer but not at a level sufficient to oxidize the metal electrode layer.

Abstract: Dielectric material compositions comprising HfO2 and a second compound are disclosed. The compositions are characterized by at least a part of the compositions being in a cubic crystallographic phase. Further, semiconductor based devices comprising such dielectric material compound and method for forming such compounds are disclosed.

Abstract: A method and system for evaluating the current-voltage characteristics of devices where negative resistance behavior is observed. More particularly the present invention relates to a method and system for evaluating accurately the electrical overstress or ESD performance of semiconductor devices during the voltage transition region (positive to negative). The method comprises applying a signal comprising at least two amplitudes within the pulse. By suitably adjusting the amplitude of the first level, such that it is high enough to trigger the device-under-test, and subsequently applying one or more levels within the same signal while keeping the device-under-test in the on-state, the device IV characteristics can be comprehensively extracted, without being limited by the system loadline.