Abstract: A charge pump circuit and method for supplying power. The charge pump circuit includes a first circuit receiving at least one low voltage signal and generating an output voltage signal. The charge pump circuit also includes a second circuit receiving a clock signal and the output voltage signal. The second circuit sends a request signal based on a comparison of the output voltage signal with two reference voltage signals, where the two reference voltage signals are derived from two supply voltage signals having a substantially constant potential difference. The charge pump circuit further includes a high voltage generator receiving the request signal and sending the two supply voltage signals to the first circuit and the second circuit. The high voltage generator adjusts the voltage potentials of the two supply voltage signals such that the voltage potential of the output voltage signal falls between the voltage potentials of the two reference voltage signals.

Abstract: Method and apparatus to obtain as-deposited polycrystalline and low-stress SiGe layers. These layers may be used in Micro Electro-Mechanical Systems (MEMS) devices or micromachined structures. Different parameters are analysed which effect the stress in a polycrystalline layer. The parameters include, without limitation: deposition temperature; concentration of semiconductors (e.g., the concentration of Silicon and Germanium in a SixGe1?x layer, with x being the concentration parameter); concentration of dopants (e.g., the concentration of Boron or Phosphorous); amount of pressure; and use of plasma. Depending on the particular environment in which the polycrystalline SiGe is grown, different values of parameters may be used.

Abstract: The present invention discloses a method for forming germanides on substrates with exposed germanium and exposed dielectric(s) topography, thereby allowing for variations in the germanide forming process. The method comprises the steps of depositing nickel on a substrate having topography, performing a first thermal step to convert substantially all deposited nickel in regions away from the topography into a germanide, selectively removing the unreacted nickel, and performing a second thermal step to lower the resistance of formed germanide.

Abstract: A MOSFET comprising a fully germano-silicided gate electrode having a high work function is disclosed. This gate electrode is formed by a self-aligned reaction process between a silicidation metal and a semiconductor material comprising silicon and germanium. Preferably, the fully germano-silicided gate is formed by a reaction between nickel and SiGe. The work function of the fully germano-silicided gate electrode can be tuned.

Abstract: A method for manufacturing a MOSFET device with a fully silicided (FUSI) gate is described. This method may be used to prevent formation of shorts between the FUSI gate and a contact to a source and/or a drain region. In particular, the method discloses the formation of an expansion volume above a gate dielectric. The volume is designed to substantially contain the fully silicided gate.

Abstract: Methods and systems are described for improving optical lithographic processing of a substrate by selecting appropriate system parameters in order to obtain a good image or print of the pattern to be obtained in a resist layer, which includes selecting a set of system parameters for an optical lithographic system having selectable system parameters, thus characterising the optical lithographic system and obtaining transferred lens pupil information. The latter is performed by obtaining, for each point of a set of points within a lens pupil of the optical lithographic system with the selected set of system parameters, a value of at least one optical parameter at a level of the substrate, the at least one optical parameter being a property of a light ray projected towards the substrate from the point of the set of points within the lens pupil. The lens pupil information then is combined with information about the mask to be used for generating the pattern in the resist layer.

Abstract: The present invention provides a system for the release of neurotransmitters and a method for the manufacturing of such a system. The system according to the present invention allows for local release of neurotransmitters and therefore makes it possible to activate single neurons. Furthermore, the system according to the invention is efficient, reproducible, and has a low power supply.

Abstract: Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.

Abstract: The present invention is related to a system and method for wideband multiple access telecommunication. In the method, a block is transmitted from a basestation to a terminal. The block comprises a plurality of chip symbols scrambled with a base station specific scrambling code, the plurality of chip symbols comprising a plurality of spread user specific data symbols which are user specific data symbols spread by using user specific spreading codes and at least one pilot symbol. In the terminal, at least two independent signals that comprise at least a channel distorted version of the transmitted block are generated. The two independent signals are combined with a combiner filter with filter coefficients which are determined by using the pilot symbol, thus a combined filtered signal is obtained. The combined filtered signal is despread and descrambled with a composite code of the basestation specific scrambling code and one of the user specific codes.

Abstract: A method for determining programming/erase conditions and a method for operating a charge-trapping semiconductor device are disclosed. Programming and erase conditions are determined such that a first net charge distribution variation profile, upon going from programmed to erased state, is substantially the opposite of a second net charge distribution variation profile, upon going from erased to programmed state.

Abstract: A method is described for extracting the spatial distribution of charge stored in a charge-trapping layer of a semiconductor device. The method comprises the steps of performing a first charge-pumping measurement on a device under test using a variation of the upper level of the pulse and performing a second charge-pumping measurement on this device using a variation of the lower level of the pulse. The data obtained is combined for extracting the spatial distribution. This is done by establishing a relation between a charge pumping current Icp and a calculated channel length Lcalc of the semiconductor device by reconstructing spatial charge distribution estimates from the charge pumping curves for multiple values of the charge pumping current Icp.

Abstract: Coding, transcoding and iterative filtering methods and apparatus are described wherein a 2D FIFO is used to implement CACLA processing, and wherein the processing methods are block-oriented. A block-by-block processed input image or input coded image, which is delayed in an arbitrary number of lines and columns, is provided such that the output image is produced in a block-by-block schedule at a reduced or minimal memory access and memory size cost. A 2D FIFO which is memory-efficient in image block coding and decoding applications is described. The 2D FIFO has an associated scheduling mechanism for enabling delay of a block-by-block coded input signal, such as an image, in an arbitrary number of lines and columns, such that the output image is produced in a block-by-block schedule.

Abstract: The invention relates to methods and apparatus suitable for executing a service or application at a client peer or client side, having a client specific device or client specific platform, with a reconfigurable architecture, said service or application being provided from a service peer or a service side. In a first aspect of the invention, the method comprises transmitting to the client peer from the server peer an abstract bytecode. The abstract bytecode is generated at the service peer by performing a compilation of an application. The abstract bytecode includes hardware bytecode and software bytecode. At the client peer, the abstract bytecode is transformed into native bytecode for the client specific device.

Abstract: The present invention is related to a method and corresponding devices for controlled transport of magnetic beads between a position X and different position Y, such that the magnetic beads are manipulated or transported by applying successively a series of N local magnetic fields which have magnetic field gradients different from 0 in the neighborhood of said magnetic beads. Each of these N local magnetic fields is generated by a single current carrying structure, in which the current density is not constant. The invention mainly points to application in the domain of biochips and microarrays, used in diagnostics, genetics and molecular studies.

Abstract: A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a different work function. The work function of each transistor type is determined by selecting a thickness of a corresponding semiconductor gate electrode and a thermal budget of a first thermal step such that, during silicidation, different silicide phases are obtained on the nMOS and the pMOS transistors. The work function of each type of transistor can be adjusted by selectively doping the semiconductor material prior to the formation of the silicide.

Abstract: A probe device is described having a substrate and a die on top of the substrate. The die has an array of stimulation/recording sites having at least one stimulation means and at least one recording means. The substrate comprising the die is folded into a cylindrical shape or a shape with a conical cross-section and, therefore, causes substantially no damage when it is implanted in tissue to be examined or treated, e.g., the brain of a patient in case of a neuro-probe device for use in deep brain stimulation.

Abstract: Methods for the quantification of hydrophilic properties of a porous material, as well as determining a depth of damage of a porous material are disclosed. An example method includes performing a first ellipsometric measurement on the porous material using a first adsorptive having a first wetting angle. The example method further includes performing a second ellipsometric measurement on the porous material using a second adsorptive having a second wetting angle, wherein the first and second wetting angles are different towards the porous material. The hydrophilic properties of the porous material are determined based, at least in part, on the first and second ellipsometric measurements.

Abstract: A method for manufacturing fully silicided (FUSI) gates and devices, in particular MOSFET devices, is described. The method includes deposition a metal layer over a semiconductor layer of a gate stack, providing a first thermal budget to allow a partial silicidation of the semiconductor layer, selectively removing a remaining unreacted metal layer, and providing a second thermal budget to allow a full silicidation of the semiconductor layer. As a result, the silicide phase can be effectively controlled.

Abstract: A method for programming a single bit nonvolatile memory cell integrated on a metal-dielectric-semiconductor technology chip. The memory cell comprises a semiconductor substrate including a source, a drain, and a channel in-between the source and the drain. The memory cell further comprises a control gate that comprises a gate electrode and a dielectric stack. The gate electrode is separated from the channel by the dielectric stack. Further, the dielectric stack comprises at least one charge storage dielectric layer. The method for programming the memory cell comprises applying electrical ground to the source, applying a first voltage having a first polarity to the drain, applying a second voltage of the first polarity to the control gate; and applying a third voltage having a second polarity opposite to the first polarity to the semiconductor substrate.

Abstract: One aspect of the invention discloses a method of determining the dopant profile of doped regions in a semiconductor substrate. A pump laser is used to create excess carriers in this semiconductor substrate. The excess carrier concentration will influence the reflection of a probe laser. From the reflected probe laser not only the bulk components but also the near-surface components are eliminated to only yield the bulk components.