Abstract: A semiconductor device and a fabrication method therefor improve electrostatic discharge (ESD) protecting property of an ESD protecting device in a fabrication method of a semiconductor device using a self-aligned silicide CMOS process. The semiconductor device has a silicide blocking portion which prevents a self-aligned silicified reaction by forming a gate electrode on drain and/or source of an ESD protecting device and simultaneously forming a dummy gate electrode which is separated from the gate electrode.

Abstract: A semiconductor memory device and method of fabricating same is provided that has a plurality of ferroelectric memory cells and reference cells. The semiconductor memory device includes a capacitor of each memory cell being the same size as that of each reference cell. A voltage applied to each reference cell is higher than a voltage applied to each memory cell to read data out of the semiconductor memory device. A method of fabricating a ferroelectric substance for a semiconductor memory device includes dissolving zirconium n-butoxide and titanium iso-proxide in 2-methoxyethanol; chelating a resultant, obtained by dissolution, with acetylacetone; adding lanthanium (La) iso-proxide to the resultant and refluxing the resultant; adding lead (Pb) acetate trihydrate to the resultant, and stirring the resultant, using a nitric acid as a catalyzer; and carrying out spin-coating and thermal treatment processes on the resultant.

Abstract: A cell structure for a low electric power static RAM is disclosed and includes a data retention voltage detector for detecting a data retention voltage, a cell load controller for controlling a cell voltage, a load resistor, an access NMOS transistor, and a drive NMOS transistor.

Abstract: An SOI device and a method for fabricating the same in which floating body effect is reduced and the performance is thus improved are disclosed, the SOI device including a semiconductor substrate; a first buried insualting film formed on the semiconductor substrate; a first conductivity type silicon layer formed on the first buried insulating film; an active region and a first conductivity type semiconductor layer formed to be isolated on predetermined areas of the first conductivity type silicon layer; second buried insulating films formed to be isolated from one another in the first conductivity type silicon layer to connect the first conductivity type semiconductor layer with the active region through the first conductivity type silicon layer; a gate electrode formed on the active region; impurity region formed in the semiconductor substrate at both sides of the gate electrode; and contact pads formed on the first conductivity type silicon layer.

Abstract: A fuse repair circuit for a semiconductor memory device includes a cell array provided with a row redundancy and a column redundancy and a fuse block for driving the row redundancy during a RAS cycle and driving the column redundancy during a CAS cycle, wherein the fuse block consists of an address input unit for selectively outputting a row address or a column address in accordance with switching signals, a plurality of fuse units, wherein redundancy information of a defective cell is programmed, for comparing an inputted address with the programmed redundancy information, and a redundancy driving unit for outputting a matching signal for driving the row redundancy or the column redundancy when the inputted address and the programmed redundancy information are identical.

Abstract: The write recovery time control circuit includes a power control signal generating circuit, a decoder circuit and a write disabling signal generating circuit. The power control signal generating circuit generates a power control signal based on a cell block address signal, at least one bit of a predecoded address signal, and a write disabling signal. The decoder circuit generates word line selection signals based on the predecoded address signal and the power control signal. The write disabling signal generating circuit generates the write disabling signal such that changes in said power control signal are delayed by a predetermined period of time.

Abstract: A thin film transistor (TFT) and a method for fabricating the same utilize a sidewall spacer and a trench to improve the reliability of the device. The TFT includes a substrate, a trench formed in the substrate, and an active layer formed on the substrate and in the trench. A sidewall spacer is formed on the active layer along at least one side of the trench. A gate insulating film is formed over the sidewall spacer and the active layer. A gate electrode is formed on the gate insulating film in the trench. Source and drain electrodes are formed in the active layer or opposite sides of the gate electrode.

Abstract: A charge coupled device is disclosed including: a well formed in a substrate, the well having a conductivity opposite to that of the substrate; a first conductivity type of BCCD region formed on the well; a first lightly doped impurity region formed in a predetermined portion of the first conductivity type of BCCD region; a heavily doped impurity region formed in a predetermined portion of the BCCD region, the heavily doped impurity region having a predetermined distance from the first lightly doped impurity region; a second lightly doped impurity region formed between the first lightly doped impurity region and heavily doped impurity region; a first polysilicon gate formed over a portion of the BCCD region, placed between the first lightly doped impurity region and heavily doped impurity region; and a second polysilicon gate formed over the first lightly doped impurity region. The realization of high speed CCD and simplification of the circuit configuration can be obtained by using one-phase clocking.

Abstract: A method of manufacturing a semiconductor device, which is designed to enhance the characteristic of a dual-gate MOS by reducing the phase difference between two gate electrodes, includes the steps of: forming a first conductivity type substrate in which a portion to be first and second gate electrodes are defined; sequentially forming a gate insulating layer and a conductive coating on the substrate; ion-implanting first conductivity type impurities into the conductive coating of a portion where the first gate electrode will be formed; ion-implanting second conductivity type impurities into the conductive coating of a portion where the second gate electrode will be formed; selectively etching the conductive coating, leaving only a portion doped with the first and second conductivity type impurities, and forming the first and second gate electrodes; and forming impurity regions in the surface of the substrate on both sides of the first and second gate electrodes.

Abstract: A receive squelch circuit detects a pulse width of an input data signal to prevent errors from occurring during detection of received data. The squelch circuit adds a function of detecting a pulse width to an input side to detect normal and abnormal pulse signals of received data and adjust the squelch circuit operations. The squelch circuit includes a plurality of current sources for each supplying a predetermined amount of current in accordance with a supplied power and a plurality of MOS transistors for detecting a pulse width of an input differential data signal. A plurality of voltage comparators compares the detected pulse width of the input differential data signal with a standard value and judges whether the detected pulse width is normal.

Abstract: A nozzle structure of a repair apparatus for a semiconductor package includes a funnel holder connected to a repair apparatus, a cylinder extended downwardly from the funnel holder, a vacuum tube provided along an axis of the cylinder, a vacuum absorption body housing the vacuum tube therein, and a pair of exhaust guide wall clips. A lower portion of the cylinder is compressed from four sides thereof so as to form a rectangular ending thereof which has first through fourth side walls. The vacuum absorption body is positioned between the first and third side walls. Each of the exhaust side walls is fixed to corresponding side edge lines of the first and third side walls, wherein the first and third side walls are identical in height and facing each other, the second and fourth side walls are identical in height and facing each other, and the first and third side walls are shorter than the second and fourth side walls in height.

Abstract: A frequency control circuit for an oscillator and a method therefor are disclosed and which frequency control circuit includes a flash cell having a cell transistor, a switching unit for outputting a first voltage to the flash cell in the program mode in accordance with an enable signal and outputting a second voltage in the read mode, a write driver for outputting a program voltage to the flash cell in the program mode in accordance with the enable signal, a bias unit for supplying a current to the flash cell in the read mode in accordance with the enable signal and generating a frequency control voltage which is proportional to a threshold voltage of the flash cell, and an oscillator for varying the frequency in accordance with the thusly generated frequency control voltage.

Abstract: Method for fabricating a semiconductor device, is disclosed, in which a grain size is made coarse for forming a thin film with a low resistance, including the steps of (1) depositing an insulating film on a substrate, (2) depositing a silicon layer on the insulating film, (3) depositing an amorphous metal nitride film on the silicon layer, and (4) heat treating the amorphous metal nitride film to alter into a crystalline pure metal film.

Abstract: Method for etching an oxide film in a plasma etching system, specifically in a high concentration plasma etching system, is disclosed, in which a mixture of new etching gas chemistry of first, second and third gases is used in forming an oxide film suitable to an integrated circuit with a high device packing density, for improving an etch rate and an etch selectivity of the oxide film to a sub-layer, the mixture gas consisting of CHF.sub.X /C.sub.a HF.sub.b /C.sub.Y F.sub.Z, CHF.sub.X /CH.sub.b F/C.sub.Y F.sub.Z or CHF.sub.X /CH.sub.a F.sub.b /C.sub.Y F.sub.Z.

Abstract: A multi-step dry-etching method that sequentially employs plasma etching and reactive ion etching process steps to form the pairs of adjacent, doped polysilicon gate electrodes of a twin-well CMOS device. The initial dry-etching process step uses to best advantage the speed of plasma etching to rapidly form pairs of adjacent p- and n-type gate-precursor features with substantially vertical sidewalls from the upper 50-80% of a doped polysilicon layer which lies on an insulating film. The gate-precursor features and, subsequently, the gate electrodes are formed from pairs of adjacent p- and n-type regions within the doped polysilicon layer which lie over pairs of adjacent n- and p-wells (the twin wells of the CMOS device), respectively, within a substrate. The subsequent dry-etching process step uses reactive ion etching to complete the formation of the pairs of adjacent, doped polysilicon gate electrodes from the remaining 50-20% of the etched, doped polysilicon layer without over-etching the insulating film.

Abstract: Semiconductor device and method for fabricating the same, is disclosed, which can maintain a threshold voltage constant despite of decreased channel width, the device including a first, and a second conductive type wells in a substrate, a first, and a second gate insulating films on the first, and the second conductive type wells, a first gate electrode on the first gate insulating film, the first gate electrode being doped with a second conductive type except for edges of the first gate electrode in a channel width direction counter doped with a first conductive type, a second gate electrode on the second gate insulating film, the second gate electrode being doped with a first conductive type except for edges of the second gate electrode in a channel width direction counter doped with a second conductive type, and isolating regions formed between the first, and second conductive type wells, the first, and second gate insulating films, and the first, and second gate electrodes.

Abstract: An improved substrate voltage (VBB) generation circuit is disclosed. The circuit reduces variations in VBB (.DELTA.VBB) caused by variations (.DELTA.VCC) in a system voltage (VCC) by making a threshold voltage (Vt) of a logic element, e.g., an inverter of in a buffer, more sensitive to .DELTA.VCC. In contrast, the conventional art had attempted to reduce .DELTA.VBB by making the Vt of the logic element less sensitive to .DELTA.VCC. Two features of the improved logic element of the circuit contribute to the reduction of .DELTA.VBB. These features are: adopting an opposite channel ratio arrangement versus the conventional art; and incorporating additional active resistors.

Abstract: An Ethernet having an automatic detecting function of data transfer rate to efficiently manage the Ethernet, comprising a medium access controller for controlling Ethernet transfer protocol; a detector for automatically detecting a rate of data transfer received from a communication medium and driving said medium access controller to automatically control a transceiving path according to data transfer rate; an encoder/decoder enabled according to a transmitting/receiving mode selection by said medium access controller for encoding/decoding data to be suitable for the transfer protocol during data transceiving; and a data transceiver enabled according to a transmitting/receiving mode selection by said medium access controller and for transmitting and/or receiving the data to and/or from the communication medium during the data transceiving.

Abstract: A fabricating method of a multi-level wiring structure for a semiconductor device that improves the resolution of photoresist film pattern by reducing a photoresist film and is capable of fabricating a semiconductor device of a high reliability by using an improved via hole mask includes the steps of sequentially forming a first insulating film, a first etching stop film, a second insulating film and a second etching stop film on a lower conductive layer pattern, forming a trench by etching the second etching stop film, the second insulating film and the first etching stop film which corresponds to an upper conductive layer pattern, forming a photoresist film on an entire upper surface of the resultant semiconductor substrate so that a thin photoresist film at about 1000-3000 .ANG.

Abstract: A CMOS (Complementary Metal Oxide Semiconductor) digital level shift circuit converts a first source voltage which ranges from Vcc to the ground, into a second source voltage which ranges from Vdd to the ground. The circuit includes an inverter and a latch circuit. The latch circuit includes a latch unit and a voltage distributor having a plurality of PMOS and NMOS transistors. The plurality of MOS transistors are serially connected in the voltage distributor, whereby the second source voltage which is higher than the channel breakdown voltages of the respective MOS transistors, is externally output.