Abstract: A semiconductor device and a method of fabricating the same are disclosed. The method includes the steps of forming an anti-oxidation layer on a substrate, forming an oxidizable layer on portions of the anti-oxidation layer to expose a portion of the anti-oxidation layer, varying a size of the exposed portion of the anti-oxidation layer by oxidizing at least a portion of the oxidizable layer, and forming a trench in the substrate according to the size of the exposed portion of the anti-oxidation layer. The semiconductor device includes an anti-oxidation layer formed on a substrate an oxidation layer formed on portions of the anti-oxidation layer by oxidizing at least a portion of an oxidizable layer, so as to define an isolation region of the semiconductor device, a trench formed in the substrate using the oxidation layer, and a field oxide layer formed in the trench.

Abstract: A solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency are disclosed, the solid-state image sensor having an HCCD and VCCDs including a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region of the second conductivity type; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.

Abstract: A memory module having a module control circuit which is capable of decreasing an operational current by configuring a 1BANK 4M.times.64 module using 16M DRAMs (1K Refresh.times.16) and reducing the number of operational devices. The module control circuit decodes externally inputted eleventh and twelfth address signals and outputs control signals in accordance with one of a plurality of column address strobe signals and a row address strobe signal, and a plurality of DRAMs in a memory unit are selected by the control signals from the module control circuit and are parallely connected for performing a data write and read operation in accordance with externally inputted first through tenth address signals, a write enable signal, an output enable signal, and the column address strobe signals.

Abstract: A data protection circuit is provided in a semiconductor memory device equipped with a row address decoder decoding a row address signal and selecting a word line, a column address decoder decoding a column address signal and selecting a bit line, and a memory cell array writing and reading to and from a memory cell in accordance with data selection signals outputted respectively from the row address decoder and the column address decoder.

Abstract: A b-bit digital and analog converter of the present invention is relatively simple and non-expensive and monotonic with relatively high differential and integral non-linearities. The converter uses weighed current ratio to achieve decrease the number of current cells to provide a cumulative current which corresponds to the digital value on the input data bus. The converter includes preferably a plurality of upper current cells, at least one unit current cell and at least one lower current cell. The currents produced by the upper, lower and unit current cells have a predetermined weighed current ratio, and the number of the upper, unit and lower current cells are based on the weighed current ratio. Further, the plurality of upper current cells have a prescribed layout, and includes a group of cells where each current cell has reverse layout orientation compared to adjacent cells.

Abstract: A multi-layer semiconductor having a semiconductor substrate, a first gate electrode formed over the substrate, first source and drain electrodes in the substrate on both sides of first and second gate electrodes, the second source and drain electrodes connected to the semiconductor layer. The method includes the steps of forming the first gate electrode over the semiconductor substrate with a first insulating layer inbetween, forming the first source and the first drain electrodes in the substrate on both sides of the first gate electrodes, forming a semiconductor layer over the first gate electrode with a second insulating layer therebetween, forming a second gate electrode on the semiconductor layer, and forming second source, and drain electrodes connected to the semiconductor layer.

Abstract: A thin film transistor and a fabrication method thereof which are capable of increasing an ON/OFF current ratio and simplifying a fabrication process by eliminating a masking process. The thin film transistor includes a substrate, an active layer formed on the substrate, a U-shaped gate electrode formed on the active layer and the substrate and having an opening portion inwardly extended from one edge surface thereof, an offset region formed in the active layer matching with the opening portion, and impurity regions formed within the active layer at both sides of the gate electrode.

Abstract: A thin film transistor and its fabrication method are disclosed wherein the thin film transistor includes a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a membrane layer formed on a portion of the active layer and defining an offset region in the active layer, a gate insulation layer formed on portions of the membrane layer and the active layer, a gate electrode formed on a portion of the gate insulation layer, and a source region and a drain region formed in the active layer.

Abstract: Method for fabricating a semiconductor device, is disclosed, which is suitable for improving a resistivity, including the steps of forming a silicon layer on a substrate, forming a crystalline metal silicide layer on the silicon layer, forming an amorphous metal silicide layer by injecting ions into the crystalline metal silicide layer, and crystallizing the amorphous metal silicide by heat treating the amorphous metal silicide.

Abstract: An overdriving control circuit includes a comparator for receiving a sense amplifier enable signal and comparing a voltage of bit line or bit bar line with a reference voltage, and a sense amplifier driving unit for logically combining the sense amplifier enable signal and an output signal of the comparator and outputting a control signal of a switch which selectively supplies an internal voltage and an external voltage. The circuit senses a variation of the external voltage or a bouncing of source voltage and controls the overdriving region, thereby obtaining a sufficient overdriving region and accelerating the operation of a sense amplifier.

Abstract: A power-up circuit for a semiconductor memory device includes an external supply voltage level detector for detecting an external supply voltage level received from an exterior, and generating an external supply voltage detection signal when a predetermined voltage level is detected, an internal supply voltage level detector for detecting an internal supply voltage level and generating an internal supply voltage detection signal when a predetermined voltage level is detected, and a power-up signal generator for receiving the internal and external supply voltage detection signals and generating a low level power-up signal at a falling edge of the internal supply voltage detection signal. The circuit prevents an access of the external device, thereby preventing the generation of an excessive current such as a latch-up caused by an instability at the internal nodes and the unstable operation of the internal circuit.

Abstract: 052450152 A power noise preventing circuit for a microcontroller unit (MCU) is provided that prevents an erroneous operation of the MCU caused by power supply noise. The power noise preventing circuit for the MCU can include a power fail detecting circuit that controls a power fail signal by comparing supplied power to a preset fail voltage of a MCU and a system clock generating circuit that receives a clock signal and generates a first system clock signal that determines a state of a system. A clock freezing and synchronizing circuit fixedly outputs a second system clock signal at a state of the first system clock signal when the power falls below the preset fail voltage and the power fail signal is enabled. The clock freezing and synchronizing circuit further outputs the second system clock signal synchronized with the first system clock signal when the power fail signal is disabled.

Abstract: A semiconductor device and a fabrication method are disclosed which are capable of preventing a charge-up phenomenon which occurs during a plasma process, and the semiconductor device includes a center portion of a semiconductor device having a passing through portion and a blocking portion and formed on the center portion of the semiconductor substrate, and a peripheral portion having a pad and a discharging portion formed near the pad and connected with the ground.

Abstract: A method for fabricating a flash memory cell includes forming first gate insulating films and polysilicon layers in succession on a substrate, wherein the first gate insulating films and the polysilicon layers extend in a first direction, and forming buried regions in the substrate under portions of the polysilicon layers. The method includes forming second insulating films, control gates, and cap insulating films in succession on the substrate and the polysilicon layers, and forming first sidewall spacers at both sides of the control gates. The method further includes forming floating gates by patterning the polysilicon layers using the first sidewall spacers as masks, forming field insulating films between the floating gates, and forming erasure gates on the field insulating films between the floating gates.

Abstract: An ESD (Electro-Static Discharge) protection circuit includes a semiconductor substrate having an active region and field regions, isolating films formed in the field regions, a gate insulating film formed on the active region, and a gate electrode formed on the gate insulating film, first and second heavily doped impurity regions formed in a surface of the semiconductor substrate at sides of the gate electrode, a plurality of dummy gate electrodes formed on the second heavily doped impurity region and offset from the gate electrode, insulating sidewalls formed at the sides of the gate electrode and at sides of each of the dummy gate electrodes, and salicide films formed on a surface of the gate electrode, on surfaces of each of the dummy gate electrodes and on a surface of the first heavily doped impurity region.

Abstract: A method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability is disclosed, including the steps of forming an insulating film having a contact hole on a semiconductor substrate; forming a barrier metal layer on the insulating film including the contact hole; and forming a metal line layer on the barrier metal layer with a CVD method using a high density plasma.

Abstract: A liquid crystal display driver includes a shift register for shifting stored R, G and B data and outputting load signals, a first latch having a plurality of channels for holding and outputting the R, G and B data, a bit converter for converting a number of bits of each R, G and B data outputted from the first latch, a multiplexer for selectively passing voltages outputted by the bit converter upon application of the load signals outputted by the shift register, a decoder for selecting and sequentially outputting an externally supplied voltage in response to an output of the multiplexer, a demultiplexer for demultiplexing output signals of the decoder upon application of the load signals, a second latch for storing and outputting output signals of the demultiplexer,and an output buffer for transmitting output signals of the second latch to a liquid crystal display panel.

Abstract: The present invention relates to a high speed empty flag generator and a method of generating a high speed empty flag which are achieved by generating a pre-empty flag in a clock ahead of a read address which is identical to a write address and by generating an empty flag as soon as a read address identical to the write address is generated after an elapse of one clock. The present invention includes a subtracter generating upper N-1 bits of a value resulted from subtracting 1 from a write address of N bits, a pre-empty flag generator generating an pre-empty flag when an output of upper N-1 bits of a rear address of N bits and an output of N-1 bits of the subtracter coincide by comparison, and a main empty flag receiving said pre-empty flag wherein the main empty flag generator generating an empty flag at a generating point of a first read signal after the pre-empty flag.

Abstract: A system for programming a nonvolatile memory includes a plurality of memory cells each having a field effect transistor with a control gate, a drain, a source, and a charge storage region, voltage sources for applying preset voltages pertinent to a threshold level to the source, the drain, and the control gate in each of the memory cells, a monitor for monitoring a current flowing through a channel in each of the memory cells, and a controller for stopping at least one of the voltages applied to the source, the drain, and the control gate in each of the memory cells when the monitor senses that the current flowing through the channel in the memory cell reaches a reference current.

Abstract: A method of fabricating a capacitor of a semiconductor device is disclosed including the step of forming a lower electrode layer on a semiconductor substrate, and a dielectric on the lower electrode layer, a part of the lower electrode layer, a part of the upper electrode layer adjacent to the dielectric of the capacitor including the upper electrode on the dielectric, or all of them containing oxygen.