Abstract: A method of fabricating a semiconductor device having a memory device region and a logic device region on a substrate includes the steps of forming first and second gate lines on the substrate at the memory device region and the logic device region, respectively, forming a sidewall insulating layer on both sides of each of the first and second gate lines, forming a plurality of impurity regions in the substrate, forming a silicon nitride layer on the memory device including the first gate lines, forming a silicide layer on the second gate line and impurity regions at the logic device region, and forming an oxide layer on an exposed surface excluding portions over each one of the impurity regions at the memory region and the logic device region, respectively.

Abstract: An electrode passivation layer of a semiconductor device and a method for forming the same having improved corrosion-resistance and oxidation-resistance are disclosed, the electrode passivation film including a semiconductor substrate; a conductive layer pattern formed on the semiconductor substrate; and an amorphous passivation film formed on the conductive layer pattern.

Abstract: A metal wire forming method for a semiconductor device includes the step of forming a first insulator film over a substrate having at least a second insulator film formed thereon and a first conductive layer formed on the second insulator film. Next, a photosensitive film is formed on the first insulator film, and the photosensitive film is exposed and developed according to a contact hole pattern. This exposes a portion of the first insulator film, and the exposed portion is then etched using the photosensitive film as a mask to form a contact hole in the first insulator film. The method further includes the steps of exposing and developing the photosensitive film according to a trench pattern which includes the contact hole pattern, and etching the first insulator film using the photosensitive film as the mask so that a trench having a predetermined depth is formed in the first insulator film and the first conductive layer is exposed via the contact hole.

Abstract: The invention relates to a fabrication method of a semiconductor device having dual gates, and more particularly to a fabrication method of dual gates which respectively have a gate insulating film having a different thickness, which includes the steps of providing a semiconductor substrate having a first region and a second region; sequentially forming a first insulating film and an oxidizable film on the first region of the substrate; and forming a second insulating film on the second region of the substrate. Since, when forming the second insulating film, the oxidizable film becomes an oxide film, which oxide film is combined with the first insulating film, thus forming the first gate insulating film, the first gate insulating film is formed thicker than the second gate insulating film in accordance with a simplified oxidation process.

Abstract: A dual gate MOSFET fabrication method includes the steps of forming a first insulation layer on a semiconductor substrate, forming a first polysilicon layer on the first insulation layer, forming a first photoresist pattern on the first polysilicon layer, forming a first gate by sequentially etching the first polysilicon layer and the first insulation layer by using the first photoresist pattern as a mask, removing the first photoresist pattern, forming a second insulation layer on the semiconductor substrate and the first gate, forming a second polysilicon layer on the second insulation layer, forming a second photoresist pattern on the second polysilicon layer, and forming a second gate by etching the second polysilicon layer and the second insulation layer by using the second photoresist pattern as a mask.

Abstract: A thin film transistor includes a first insulating layer and a first conductive layer formed on a semiconductor substrate, a second insulating layer, a second conductive layer and a third insulating layer sequentially formed on the first conductive layer, a contact hole formed in the second insulating layer, second conductive layer and third insulating layer, a gate insulating layer formed along the sidewall of the contact hole, and a third conductive layer formed on the contact hole formed with the gate insulating layer thereon and surface of the third insulating layer to be used as a channel region and a source region by implanting an impurity, in which a drain region, a gate electrode and the source region are stacked, or vertically aligned, on the substrate to allow a cell to occupy a small area for accomplishing high packing density of the cell and permit the gate electrode to encircle the channel region for improving a characteristic of the transistor, thereby stabilizing the cell.

Abstract: A method for controlling a memory cell capable of extending a refresh interval and lengthening a storing time of a cell data by raising a data of a high level voltage stored in the cell capacitor above Vdd, thereby reducing power consumption.

Abstract: YUV to RGB converter for converting a digital YUV signal having a Y signal, a U signal, and a V signal to a digital RGB signal having an R signal, a G signal, and a B signal according to equations:R=Y+N.sub.1 .times.VG=Y-N.sub.2 .times.V-N.sub.3 .times.UB=Y+N.sub.4 .times.Uwherein the YUV to RGB converter performs only bit shifting and adding/subtracting operations, and N.sub.1, N.sub.2, N.sub.3, and N.sub.4 are constants.

Abstract: A start-up circuit for a reference voltage generator which restarts a reference voltage generating circuit when a reference voltage drops below a predetermined level due to noises or change of a power supply voltage. The start-up circuit according to the present invention includes a reference voltage generating unit operated by an input signal and generating a reference voltage in accordance with a power supply voltage, a reference voltage sensing unit determining whether an output signal from the reference voltage generating unit is lower than a predetermined voltage level, and a start-up circuit unit determining an initial operation of the reference voltage generating unit in accordance with a reset signal and supplying the input signal to restart the reference voltage generating unit in accordance with an output signal from the reference voltage sensing unit.

Abstract: A negative delay circuit (NDC) has an NDC array operated in a high frequency. The circuit varies a number of unit delay stages at an input stage of the NDC array according to a locking fail signal in a low frequency region. The NDC can carry out a negative delay operation in a wide band even when a number of the stages in the NDC array is small. The present invention decreases a size of a chip, and in addition, reduces an unnecessary current consumption by preventing a locking from re-occurring at a stage in a back portion because the NDC array has a delay value less than one clock.

Abstract: An input buffer circuit includes a transition detecting unit for receiving an input signal, detecting a transition of the input signal, and outputting a detecting signal and a delayed input signal; a detecting signal summing unit for summing up the detecting signal and other detecting signals outputted from other transition detecting units, and outputting a plurality of summed signals; a buffer unit for transmitting the delayed input signal in accordance with the plurality of summed signals; a control signal generator for receiving one of the plurality of summed signals and a first control signal, and outputting a second control signal and a third control signal; and a write driver 204 for receiving the second and third control signals, and transmitting an output signal of the buffer unit to a cell by a trigger of the plurality of summed signals.

Abstract: Semiconductor memory device which can support a DDR SDRAM latency mode like 2.

Abstract: A semiconductor package includes a semiconductor package substrate having a frame type insulator which has a penetrating portion in a center portion of the substrate and a plurality of lead bars exposed to upper and lower surfaces of the insulator, a semiconductor chip on the semicondcutor package substrate, an upper surface of the semiconductor chip being attached to the lead bars, a plurality of pads on a center portion of an upper surface of the semiconductor chip, a plurality of wires respectively connecting the pads with an upper surface of the lead bars, and an upper cover protecting the wires, the pads and an upper surface of the semiconductor chip.

Abstract: The semiconductor chip package includes a package body with a recess and a plurality of barrier parts formed along one side thereof. Each of the barrier parts has a first region and a second region projecting from the first region, and adjacent first regions are separated by a slot. A semiconductor chip, including a reference surface having a circuit and a plurality of bonding pads formed thereon, is disposed in the recess of the package body. A conductive member is disposed in each slot, and a connecting member, associated with each bonding pad, electrically connects the associated bonding pad with a corresponding conductive member. A sealing member seals the semiconductor chip, the connecting members, and at least a portion of the conductive members in contact with the connecting members. Stacking these packages in the transverse and/or longitudinal direction further reduces their mounting area and increases the integrated capacity per unit of mounting area.

Abstract: The present invention relates to a method of isolating semiconductor devices enabling to prevent an active area from being reduced due to the increase of an isolation area by means of forming trenches, and includes the steps of forming a mask on a semiconductor substrate wherein the mask discloses field areas, forming a first and second trench in the field areas of the semiconductor substrate wherein the first trench has a larger size and a lower aspect ratio than those of the second trench and wherein the second trench has a smaller size and a higher aspect ratio than those of the first trench, depositing filling oxide on the mask and in the first and second trench by a method including characteristic of sputtering wherein the first and second trench are filled up with the filling oxide and a void is formed on a lower part of the second trench, and forming field oxide film by means of etching back the filling oxide to remain inside the first and second trench.

Abstract: A semiconductor memory device and method of fabricating the same, which improves adhesion of the lower electrode of a ferroelectric planar capacitor, and prevents inter-diffusion between the Pt electrode of the capacitor and adhesion layer placed under the Pt electrode. The semiconductor memory device includes an insulating layer formed on a substrate, a paraelectric layer formed on the insulating layer, and a conductive layer formed on the paraelectric layer.

Abstract: A fabrication method for a semiconductor memory device, which forms a capacitor over a bit line, includes the steps of forming an active region pattern on a semiconductor substrate, forming a field oxide region for electrically isolating single devices in the semiconductor substrate, forming a gate insulating film on the semiconductor substrate, forming a first conductive film to serve as a gate electrode on the gate insulating film, forming a first insulating film having a first etching characteristic on the first conductive film, and patterning the first insulating film and the first conductive film to form a plurality of word line patterns. Next a second insulating film, having the first etching characteristic, is formed over the semiconductor substrate, and is etched to form sidewall spacers at lateral walls of each word line pattern. A third insulating film is then formed over the semiconductor substrate, and removed from regions where a bit line is to be formed.

Abstract: A metal-oxide-semiconductor (MOS) device in which the nonuniform dopant concentration in the channel region is obtained by means of ion implantation through a polysilicon gate electrode of nonuniform cross section, which is itself obtained by oxidizing the polysilicon using a semirecessed LOCOS process.

Abstract: A semiconductor device includes a semiconductor substrate having an active area including first and second impurity regions of a transistor, a gate formed over the active area of the semiconductor substrate and isolated from the semiconductor substrate, a first insulating interlayer formed on the semiconductor substrate and having first and second contact holes exposing the first and the second impurity regions, respectively, a capacitor having a storage electrode and a plate electrode, the storage electrode being connected electrically to the first impurity region through the first contact hole, a bit line contact pad connected electrically to the second impurity region through the second contact hole, a second insulating interlayer formed on the plate electrode and having a third contact hole exposing the bit line contact pad, and a bit line formed on the second insulating interlayer and in contact with the bit line contact pad through the third contact hole.

Abstract: A method of forming a twin well includes the steps of: forming a field oxide layer on a semiconductor substrate to define active regions of a device, and forming a first mask which exposes a predetermined active region of the semiconductor substrate; ion-implanting a first conductivity type impurity into the exposed region of the semiconductor substrate using the first mask as an ion implantation mask, to form a first well; ion-implanting a second conductivity type impurity to penetrate the first mask, to form a buried region which is self-aligned with the first well and comes into contact with the bottom of the field oxide layer; removing the first mask, and forming a second mask which is to expose the first well of the semiconductor substrate; and ion-implanting a second conductivity impurity into the exposed region of the semiconductor substrate to levels deeper and shallower than the buried region using the second mask as an ion implantation mask, to form a second well including the buried region.