Abstract: An interconnection fabricating method for a semiconductor device includes the steps of forming an interconnection layer on a semiconductor substrate, forming a first photoresist layer on the interconnection layer, forming an insulation layer on the first photoresist layer, forming a second photoresist layer pattern on the insulation layer, sequentially etching the insulation layer and the first photoresist layer to obtain an insulation layer pattern and a first photoresist layer pattern, and removing the second photoresist layer pattern, removing the insulation layer pattern using dry etching, and forming an interconnection layer pattern by selectively etching the interconnection layer.

Abstract: This invention relates to a nonvolatile ferroelectric memory device which includes main cell array arranged in columns of even number, reference cell array arranged in two columns, a plurality of cell array blocks in which a plurality of pairs which consist of said main cell array and said reference cell array are arranged, SWL word line driver arranged along said column in parallel, and control block connected between both ends of said columns in order to control other cell array block neighboring with said cell array blocks.

Abstract: A solid state image pickup device including implanting impurity ions into a planarizing layer and/or a microlens layer thereon for changing a refractive index thereof, and method for fabricating such a device. The planarizing layer and the microlens layer are formed over components of the solid state image pickup device including a plurality of photoelectric conversion regions and charge coupled device (CCD) regions, each charge coupled device transferring an image charge generated in the photoelectric conversion regions in one direction.

Abstract: Static random access memory (SRAM) cell is disclosed, which is suitable for high packing density and cell stabilization, including a substrate, a wordline formed over the substrate, including two parallel legs having gates of first and second access transistors, respectively, gates of first and second drive transistors formed between the two parallel legs, and an active area defined in a surface of the substrate under the gates of the first and second access transistors and gates of the first and second drive transistors.

Abstract: A flash memory is disclosed including a second conductivity-type substrate having first conductivity-type first and second impurity regions spaced apart from each other by a predetermined distance; a second conductivity-type floating gate formed above part of the first impurity region; a first conductivity-type floating gate formed over the second conductivity-type floating gate; and an insulating layer and first conductivity-type control gate sequentially formed on the first conductivity-type floating gate.

Abstract: Method for fabricating a COB type semiconductor package, which is suitable for simplifiing a process from wire bonding to milling, including the steps of (1) mounting chips on a COB film having a plurality of bond holes formed therein, (2) electrically connecting the chips to inside portions of the COB film through the bond holes, (3) placing a solid state EMC(Epoxy Molding Compound) on a top surface of each of the chips, and (4) heating the solid state EMC so that the EMC covers wires and the chips.

Abstract: A transconductance control circuit includes a differential input terminal wherein first and second differential MOS transistor pairs are parallel connected, a first current source connected between a supply voltage terminal and respective sources of the first differential MOS transistor pair and for providing a first bias current, and a second current source connected between a source of the second differential MOS transistor pair and ground, and for providing a second bias current. The circuit further includes a current detector for detecting respective bias currents of the first and second current sources and the current detector includes one DC path which leads from Vdd to Vss. The circuit decreases a transconductance variation by varying an operational voltage of a differential MOS transistor pair at an RTR differential input terminal and decreases power consumption while decreasing chip size.

Abstract: A reference voltage generation circuit which is capable of generating a reference voltage having multiple steps by using a periodic response characteristic of a chaotic circuit. The circuit includes a first sample/hold unit for sampling and holding a periodic output voltage V3 in accordance with a first clock signal CLK1 from an externally connected clock signal generation unit, a second sample/hold unit for sampling and holding an output voltage V3' from the first sample/hold unit in accordance with a second clock signal CLK2 from the externally connected clock signal generation unit, a non-linear unit for receiving voltage V4 from the second sample/hold unit and outputting a non-linear voltage V2 signal having a sawtooth-shaped transfer characteristic, and an addition unit for adding the non-linear voltage signal V2 from the non-linear unit and an externally applied voltage signal V1 and outputting the periodic output voltage V3.

Abstract: A method of fabricating a nonvolatile memory device having a substrate, includes the steps of forming a plurality of bit lines in the substrate, forming a plurality of field oxide layers on the substrate perpendicular to the bit lines, forming a gate insulating layer on an entire surface of the substrate including the bit lines and the field oxide layers, forming a plurality of floating lines on the gate insulating layer between the bit lines, forming a dielectric layer on the entire surface of the semiconductor substrate including the floating line's and the gate insulating layer, forming a plurality of word lines between the field oxide layer perpendicular to the bit lines, forming sidewall spacer at both sides of the word lines, selectively removing the dielectric layer and the floating lines using the word lines and the sidewall spacer as masks to form a plurality of floating gates, forming a tunneling layer at both sides of the floating gates, and forming a plurality of program lines between the bit line

Abstract: A signal compressing apparatus is disclosed, which controls output signal in case of exceeding input signal to increase transmission efficiency and obtains stable output due to temperature compensation. The signal compressing apparatus includes an amplifier for amplifying an input signal applied through an input resistor connected to an input terminal at a constant gain, and a gain controller for rectifying only a specific band signal of output signals of the amplifier between the input terminal of the amplifier and an output terminal thereof, compensating temperature of the rectified signal, and outputting a control signal to allow the gain of the amplifier to be constant.

Abstract: A bottom lead frame and a bottom lead semiconductor package embodying the invention are capable of forming a multiple row pin structure. The bottom lead frame includes a plurality of first leads, and a plurality of second leads, where each lead has a bottom lead portion and an inner lead portion that is upwardly bent from the bottom lead portion. The first leads and second are arranged on opposite sides of a central portion. Each of the first leads is inserted between a pair of neighboring second leads. The bottom portions of the second leads are arranged outwardly of the bottom portions of the first leads. A lead support bar may be connected to the inner portions of the first and second leads to support the first and second leads. A semiconductor chip may be mounted on upper surfaces of either the first or the second leads.

Abstract: A solid state image sensor includes a photodiode, a vertical charge coupled device positioned to a side of the photodiode for transmitting charges generated in the photodiode, a first polygate extending in a horizontal direction and partly overlapping the vertical charge coupled device, and a second polygate extending in a horizontal direction, partly overlapping the vertical charge coupled device and having a second polygate extension, wherein the second polygate extension extends for substantially an entire length of the side of the photodiode.

Abstract: A method of planarizing a multilayer semiconductor wiring structure includes the steps of forming a planarization layer on a substrate, forming a first conductive line pattern over the planarization layer, forming an insulation layer over the first conductive line pattern and the planarization layer, forming holes in the insulation layer to selectively expose portions of a top surface of the first conductive line pattern, forming a second conductive line pattern over the insulation layer, over portions of the first conductive line pattern, selectively in contact with the first conductive layer through the holes, and filling the holes, and forming a passivation layer over the second conductive line pattern, wherein conductive lines of the first conductive line pattern have a width of less than approximately 2 .mu.m.

Abstract: A method of fabricating a DRAM cell and the DRAM cell include a substrate, and a bit line formed in a first direction on the substrate. A channel region is then formed on a portion of the bit line. The channel region has a lateral surface extending vertically from the bit line. A first insulating layer is formed over the substrate, excluding the channel region, and is formed on at least a portion of the lateral surface of the channel region. A gate electrode is formed on a portion of the first insulating layer, which is on the portion of the lateral surface of the channel region, and a word line, connected to the gate electrode, is formed in a second direction on the first insulating layer. A second insulating layer is then formed over a portion of the substrate. The second insulating layer has a contact hole which exposes the channel region. Next, a capacitor is formed on a portion of the second insulating layer and on the channel region via the contact hole.

Abstract: A nonvolatile ferroelectric memory having a pair of split word lines rather than a word line and a plate line simplifies the manufacturing process and allows high density integration. The memory includes a first and second transistors, each having a source, a drain and a gate. The gate of the first and second transistors are coupled to the corresponding split word lines. A first ferroelectric capacitor has an electrode connected to the source of the first transistor and the other electrode is connected to one of the split word lines coupled to the gate of the first transistor. A second ferroelectric capacitor has an electrode connected to the source of the second transistor and the other electrode is connected to the other split word line which is coupled to the first of the second transistor.

Abstract: A flash memory device of the present invention increases a speed of reading data. The conventional art has a problem of losing data due to data collision when increasing the data reading speed by making an operation of an external clock signal fast. However, the flash memory device of the present invention has an advantage of preventing the data loss even in a fast data reading operation by using a temporary buffer and an output control signal for outputting data in the data reading operation.

Abstract: A coding circuit of the present invention converts n-bit binary data word at a prescribed clock cycle (t) into to an m-trit ternary code word, where n and m are integers and n.gtoreq.m. The coding circuit includes an (x) number of storage elements or latches and a (y) number of coders, each storage element or latch receiving (m.div.x) bits of the binary data word at a clock cycle of (t.div.x). After a prescribed delay period, a corresponding storage element or latch outputs the sampled bits to a corresponding coder at an increasing or decreasing edge of the clock signal. Each coder codes the sampled bits to (m.div.y) ternary code. The each of the coders outputs (m.div.y) ternary code onto a corresponding signal line of a bus. Hence, the coding circuit outputs m-trit ternary code word onto the bus. An exemplary coding circuit is illustrated where n=8, m=6, t=25 MHz, x=2 and y=2, and D flip-flops are used for the storage elements and latches.

Abstract: The present invention relates to a ball grid array (BGA) semiconductor package member and its manufacturing method employing a carrier frame and a substrate, and to a method of manufacturing a BGA semiconductor package using the BGA semiconductor package member. In manufacturing the conventional BGA semiconductor package, conventional package manufacturing equipment cannot be employed because a boat is used during processing which requires additional equipment, and thus increases the costs of production. However, a BGA semiconductor package manufacturing method employing a carrier frame and substrate according to the present invention is compatible with conventional semiconductor package manufacturing equipment.

Abstract: Wells of a semiconductor device suitable for achieving high integration, and a method for forming the same are disclosed. The wells of a semiconductor device include a first conductivity type semiconductor substrate where a cell region and a periphery region are defined, a second conductivity type shield region in the entire cell region and in the entire periphery region at a depth below surface of the semiconductor substrate, a first conductivity type well on the second conductivity type shield region beneath the surface of the semiconductor substrate, a second conductivity type shield sidewall formed in the second conductivity type shield region and the first conductivity type well at border of the cell and periphery regions, a first conductivity type buried region formed at the second conductivity type shield region in the periphery region, and a second conductivity type well on the first conductivity type buried region in the first conductivity type well.

Abstract: A pulse generating circuit for a dynamic random access memory includes a fixed pulse generating unit receiving an input signal and generating an output pulse signal of a fixed width, a pulse delay unit receiving the input signal and delaying an output pulse signal of a variable width, a pulse width detecting unit receiving the input signal and an inverted input signa, outputting a first flag signal displaying a low pulse width by detecting the low pulse width of the input signal, and outputting a second flag signal displaying a high pulse width by detecting the high pulse width of the input signal, a NOR gate performing a logical operation on the first flag signal and the second flag signal and outputting a third flag signal, and a multiplexer coupled to the fixed pulse generating unit, the pulse delay unit, and the pulse width detecting unit and outputting an output pulse signal in accordance with the third flag signal.