Abstract: A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

Abstract: An amplifier capable of being tuned to provide linear gain over a selected input signal range is disclosed herein. The amplifier includes an input stage for receiving an input signal. The amplifier further includes a tuning circuit, connected between the input stage and an amplifier output stage, for controlling gain of the amplifier by adjusting a tuning current supplied to the amplifier output stage. The tuning circuit may be realized with a differential transistor pair connected to a pair of transistors within the output stage. In a preferred implementation the input and output stages are arranged in a folded-cascode configuration so as to improve the output impedance and input common-mode signal range of the amplifier.

Abstract: A capacitor is provided including first and second electrodes formed from portions of the lead frame structure used in conventional integrated circuit packaging. The electrodes are encapsulated with dielectric molding material which provides dielectric insulation between the electrodes. A low power capacitively-coupled digital isolator circuit is also provided. The circuit employs a pair of the lead frame capacitors of the present invention and includes differential driver and receiver circuits. The receiver can also include an optional filter for increasing noise and glitch immunity.

Abstract: A switched capacitor lowpass filter is disclosed having four cascaded general purpose switched capacitor active filter blocks that combine with each other to produce a particular overall transfer function that has high gain selectivity and substantially linear phase response characteristics. The filter can also include a clock input which allows a user to select the cut-off frequency of the filter. The filter's characteristics are tailored in accordance with a method which: (1) introduces a notch frequency into the filter's gain characteristics, so as to improve the filter's gain selectivity near the cut-off frequency, and (2) linearizes the phase response characteristics of the overall filter, without modifying the magnitude of the gain of the notch-containing filter.

Abstract: Control circuits for a switching voltage regulator circuit which uses magnetic flux sensing are provided. These circuits can be used to improve output voltage regulation by reducing parasitic effects inherently present in magnetic flux-sensed feedback switching voltage regulator designs.

Abstract: A power efficient circuit for charging the gate of a transistor switch to a charge-pumped voltage level in excess of a supply rail voltage is provided. The circuit includes a current-controlled oscillator which generates an oscillating waveform that drives a capacitive charge-pump circuit. The circuit monitors the gate voltage of the transistor switch and reduces the frequency of the oscillating waveform, thereby reducing power consumption, when the gate voltage exceeds a frequency switching value indicating that the transistor switch has been sufficiently turned so as to allow the circuit to enter a micropower mode.

Abstract: A highly DC accurate filter network capable of implementing a transfer function of arbitrary complexity is disclosed herein. The filter network includes a differential integration and summation network having a first input port connected to an input terminal of the filter network, a second input port, and an output port. A filter circuit having a predefined transfer function is connected between the output port and an output terminal of the filter network. In addition, a feedback path connects the output terminal to the second input port of the differential integration and summation network. During operation of the filter network the filter circuit cooperates with the differential integration and summation network so as not to affect the amplitude of the DC component of an input signal applied to the input terminal. This results in high DC accuracy even if the filter circuit is implemented using, for example, active components.

Abstract: A driver circuit and method for alternately driving first and second power transistors is provided. The driver circuit includes shoot-through reduction circuitry for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit includes a circuit to prevent transient signals from said power transistors from affecting the operation of the driver circuit.

Abstract: A power supply and control circuit is provided for driving a fluorescent lamp from a low voltage DC power source such as a battery. A DC-to-AC inverter coupled to a switching regulator converts low DC voltage into a higher AC voltage for driving the fluorescent lamp. The lamp is included in a feedback loop which includes a circuit for producing a feedback signal indicative of the magnitude of current conducted by the lamp. The feedback signal is applied to the switching regulator to produce in the lamp a regulated current and, hence, a regulated lamp intensity. The magnitude of the lamp current can be adjusted to enable the intensity of the fluorescent lamp to be smoothly and continuously varied (without "dead-spots" or "pop-on") over a chosen intensity range, including if desired, from substantially full OFF to full ON. A method for driving a fluorescent lamp from a low voltage DC power source is also provided.

Abstract: A segmented DAC is described in which the outputs of a pair of subword DAC circuits are summed by modulating the offset voltage of a differential buffer amplifier. Also described are various alternative DAC embodiments and an operational amplifier input stage in which modulation of the offset voltage of a differential amplifier responsive to a digital signal is accomplished using interpolation techniques for eliminating errors in linearity and monotonicity arising from component inaccuracies.

Abstract: A driver circuit for driving top and bottom power transistors stacked between two supply terminals is provided. The driver circuit includes shoot-through reduction means for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit which can utilize a bootstrap capacitor for providing enhanced voltages to drive the top power transistor, also includes a bootstrap capacitor recharge means to monitor the output voltage of the circuit so as to inhibit the turning-ON of the top power transistor until the bootstrap capacitor has had sufficient time to recharge.

Abstract: Comparators for use in a semi-flash analog-to-digital converter utilize switched capacitor inputs for effecting a subtraction of charge corresponding to the subtraction of voltages to obtain the most significant bit comparisons and least significant bit comparisons. In a preferred embodiment, a 6-input switched-capacitor comparator is employed in which an analog input signal, a most significant reference TAP, and the output from a digital-to-analog converter are sequentially coupled through a first capacitor to the input of an inverting amplifier. A second plurality of input terminals sequentially connects one-half the least significant bit reference potential, 0 volts, and a least significant reference voltage TAP through second capacitive means to the input of the inverting amplifier. One comparator can thereby perform both a most significant bit comparison and a least significant bit comparison in a semi-flash mode of operation.

Abstract: A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

Abstract: A method and circuit for increasing the output impedance of an inactive amplifier is provided. The method and circuit allows an increased number of amplifiers to be coupled in parallel to a single transmission line for distributing a plurality of video or other electrical signals to a remote location. The method and circuit increasing the impedance of an amplifier feedback network during inactive operation using a bootstrapping technique (i.e., by driving the feedback network) so as to increase the overall impedance of the amplifier during such operation.

Abstract: An integrated circuit having diffused resistors formed in a low impurity concentration isolation region.

Abstract: Control circuits for a switching voltage regulator circuit which uses magnetic flux sensing are provided. These circuits can be used to improve output voltage regulation by reducing parasitic effects inherently present in magnetic flux-sensed feedback switching voltage regulator designs.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.

Abstract: A three terminal control circuit for a low dropout voltage regulator having a PNP pass transistor is provided. The control circuit is capable of pulling the base drive point down to a voltage of 3.0 volts or less to permit a current limiting resistor to be inserted between the base drive point and the base of the PNP pass transistor. The control circuit includes a pair of small-valued capacitors for providing stable operation with different output capacitors. The control circuit can also be used with p-channel FET pass transistors.

Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.