Abstract: A power efficient circuit for charging the gate of a transistor switch to a charge-pumped voltage level in excess of a supply rail voltage is provided. The circuit includes a current-controlled oscillator which generates an oscillating waveform that drives a capacitive charge-pump circuit. The circuit monitors the gate voltage of the transistor switch and reduces the frequency of the oscillating waveform, thereby reducing power consumption, when the gate voltage exceeds a frequency switching value indicating that the transistor switch has been sufficiently turned so as to allow the circuit to enter a micropower mode.

Abstract: A Schottky diode is presented which has reduced minority carrier injection and reduced diffusion of the metallization into the semiconductor. These improvements are obtained by interposing a layer comprising a mixture of silicon and chromium between the anode metallization layer and the semiconductor in a Schottky diode. The layer including chromium acts an effective barrier against the diffusion of the metallization layer into the semiconductor, and at the same time reduces the amount of minority carrier injection into the substrate. The layer including chromium requires no addition photolithograpic masks because it can be plasma etched using the metallization layer as a mask after that layer has been patterned.

Abstract: A switching regulator network is disclosed which receives an input voltage and provides a regulated constant output supply voltage. The regulator includes a pulse width modulated switching circuit which regulates the output voltage responsive to a feedback error signal. A transconductance error amplifier produces an error feedback signal which is proportional to the difference between the reference input voltage and the output voltage. The overshoot of the output supply voltage is minimized by including a means in the transconductance error amplifier to provide a higher negative slew rate current than the positive slew rate current. This is done without employing extra pins or parts in the integrated circuit.

Abstract: An electrostatic discharge protection clamp particularly useful for with bipolar and biCMOS integrated circuits include an NPN transistor formed in an isolated tub in an epitaxial layer grown on a substrate. The collector of the NPN transistor is connected to the input terminal, and the emitter of the NPN transistor is connected to the substrate. A resistor interconnects the base and the emitter. Advantageously, the P-doped base can abut the P-doped isolation region forming the tub, and the P-doped isolation region can interconnect the emitter to the substrate. Below BV.sub.CES the clamp will look like an open circuit, and above BV.sub.CES the transistor will start conducting current. The transistor will break down collector to base. Conduction of the transistor causes a voltage drop across the base-emitter junction, and when this voltage drop exceeds the base-emitter forward voltage the transistor will turn on.

Abstract: A method is provided for use with an integrated circuit which includes a npn bipolar transistor on which a variable thickness oxide layer has been formed, the method for improving the radiation hardness of the transistor comprising the steps of: removing the variable thickness oxide layer; and forming a new oxide layer on the transistor, the new oxide layer having less overall volume than the removed variable thickness oxide layer.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tube, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: A differential input amplifier stage having improved frequency compensation. Frequency compensation is achieved by cancelling one-half of the signal output of a differential error amplifier in the input stage, such that all error signals must pass through a "current-mirror" type load circuit in which a resistor-capacitor network is provided to roll off gain of the input stage.

Abstract: The surface area of a junction-isolated tub in a silicon epitaxial layer grown on a silicon substrate is increased by introducing dopant into surface portions of the tub to effectively push back the junction between the tub and the isolation region. The junction-isolation region surrounding the tub typically has a dopant concentration profile which decreases from the center of the junction-isolation region towards the junction with the tub. By increasing the surface concentration of dopant in the tub, the net dopant concentration of peripheral portions of the junction-isolation region is converted, thereby effectively increasing the size of the surface of the tub. The dopant concentration in the surface of the entire tub can be increased, or only the periphery of the tub can have increased dopant concentration, thereby maintaining the breakdown voltage of devices fabricated in the tub.

Abstract: An integrated high gain amplifier in which voltage at the high impedance output node is sensed by sensing voltage excursions which are proportional to the output voltage at another point in the circuit which is coupled to the output node to boost the gain of the amplifier.

Abstract: A new level shifting circuit is presented which does not restrict the upper limit of the common-mode input range of an operational amplifier. This is important particularly in operational amplifiers designated to operate with low power supply voltages. Significant parameters. of the operational amplifier, such as the gain and the slew rate, can be controlled without adversely affecting the common-mode input voltage range. The level shifting stage operates nondifferentially to avoid stability problems found in differential stages. A further improvement is accomplished using current balancing to achieve gain enhancement.

Abstract: A reference voltage generator is presented for use in a differential amplifier. The reference voltage provided by the generator tracks the non-signal dc conditions of a differential input stage and provides a reference voltage to a level-shifting stage so that feedforward compensation can be used to provide extended bandwidth without settling time problems.

Abstract: An operational amplifier having input and output stages with positive capacitive feedback to the output stage derived from a point in the circuit where the voltage is proportional to the output voltage.

Abstract: An integrated circuit is provided which uses a single drive signal for turning a PNP switching transistor "on" and "off." An NPN transistor provides reverse drive current to the PNP transistor's base. When the drive signal is present, the PNP switching transistor is turned "on" and is driven into saturation. The drive signal during this period also charges an integrated capacitor coupled to the base of the NPN transistor. The drive signal then is removed to turn the PNP transistor "off." Removal of the drive signal also causes the voltage developed across the capacitor to drive the base of the NPN transistor. This, in turn, causes the NPN transistor to drive the base of the PNP transistor with a reverse drive current, thus speeding up the switching of the PNP transistor from the conducting state to the non-conducting state.

Abstract: A constant current amplifier stage for a voltage comparator circuit includes a first CMOS transistor pair having a common gate terminal and a common drain terminal and a second CMOS transistor pair which functions as a load for the first CMOS transistor pair. The second CMOS transistor pair has a common gate terminal and a common drain terminal both of which are connected to the common drain terminal of the first CMOS transistor pair. The transistors are configured so that the current through the first transistor pair at null is at least twice the current through the second transistor pair at null voltage.

Abstract: An analog multiplier feedforward technique for use in the feedback loop of a switching regulator circuit is provided. The analog multiplier eliminates the necessity for the output of the error amplifier to the regulator circuit to change voltage when regulator input voltage changes, and makes "loop" gain independent of input voltage.

Abstract: The present disclosure is of a novel circuit for controlling the impedance of an integrated circuit node during power-off and transient power conditions. The circuit includes a PNP transistor having an emitter-collector circuit connected between the circuit node and a ground node. The base of the transistor is connected to the ground node by a resistance, which holds the voltage at the base of the PNP transistor near ground potential when a signal is applied to the circuit node. The resistance can be implemented with a pinch resistor or as a FET transistor. The emitter of the PNP transistor clamps the voltage at the node to a value equal to the voltage drop across the resistor plus the forward voltage drop across the emitter-base circuit of the PNP transistor, the sum of which is less than the minimally necessary base-emitter turn-on voltage of a Darlington-connected NPN transistor pair.

Abstract: A high speed BIFET junction field effect transistor is formed in an epitaxial layer of one conductivity type and includes source and drain regions of opposite conductivity type interconnected by a thin channel region of the opposite conductivity type. A thin surface layer of the one conductivity type is formed over the channel region, and a highly conductive contact is formed on the surface layer intermediate the source and drain regions. The surface contact can comprise highly doped polycrystalline silicon material with a metal layer on the surface thereof. The surface contact and the epitaxial layer underlying the channel region comprise gates for the field effect transistor. Increased speed of operation comes from the increased conductivity of the surface contact.

Abstract: Disclosed is a switched capacitor filter block having a nonlinear quality coefficient, Q, whereby quality can be enhanced while limiting the size of feedback resistors in the filter block. A pair of capacitors alternately switchably connect an input signal to the input of integrator whereby the sampling frequency is twice the switching frequency. The filter block is readily fabricated in a monolithic integrated circuit with the feedback resistors being thin-film resistors formed on the surface of the monolithic integrated circuit. Such a circuit configuration is more accurate in programming and requires only one mask step in fabrication to program.

Abstract: A clock selection circuit having a single input terminal for receiving an external clock signal and including logic means for selectively passing an external clock signal and an internal clock signal to an output. A clock detector is connected to the input terminal for generating a voltage in response to an external clock signal. The generated voltage is utilized in controlling the logic circuitry in selectively passing the external clock signal or the internal clock signal. In a preferred embodiment, the logic circuitry includes a first two input NAND gate, a second two input NAND gate, and a third two input NAND gate. One input of the first NAND gate receives the external clock signal, and one input to the second NAND gate receive sthe internal clock. The two outputs of the first and second NAND gates are connected to the inputs of the third NAND gate.

Abstract: An integrated circuit resistor adjustment network with resistors (R1, R.sub.2, R.sub.3, R.sub.4) which may be paralleled by trimming resistors (R5, R7, R6, R8, respectively) upon electrical "zapping" of Zener diodes (Z1, Z2, Z3, Z4, respectively) connected in series with the trimming resistors. The Zener diodes (Z1, Z4 or Z2, Z3) are connected in inverse series via inverse paralleled diodes (D1, D2 or D3, D4 respectively) which are non-conductive during normal operation, but conduct during higher voltage zapping operation to permit the currents for zapping the Zener diodes to bypass the resistors.