Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A method and computer program for estimating a cell delay for an integrated circuit design include steps of selecting a range of values for cell ramptime and load and a range of values for an additional cell parameter. The values for cell ramptime, load, and the additional cell parameter are arranged in a lookup table. A cell delay is calculated for each combination of cell ramptime, load, and the additional cell parameter for the lookup table.

Abstract: A system and method for evaluating multiple corner case static timing analyses. For each node within the analysis, the variability and margin of the node is used to create a risk factor that is used to identify nodes for further analysis. In some cases, a subset of nodes may be selected for static timing analysis with several additional corner cases. The variability of the node may be determined by the difference between the maximum and minimum value of the node between corner case analyses. The margin may be determined by the difference between the actual timing and the required timing. Various ratios using variability and margin may be used to identify those nodes on which to perform further analysis.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration.

Abstract: A circuit is configured as a splittable duplex memory cell or as a joinable single port memory pair based on the state of a programming layer. The programming layer has two states. In one state, the programming layer configures the circuit as a joinable single port memory pair. In the other state it configures the circuit as a splittable duplex memory cell. As such, the circuit can act as either a dual port memory cell or as two single port memory cells.

Abstract: A method of routing an integrated circuit package design includes steps of receiving as input at least a portion of an integrated circuit design including a differential pair of two electrical conductors, calculating a value of length mismatch between the two electrical conductors, calculating an added trace length to compensate for an impedance discontinuity of a shorter one of the two electrical conductors, and extending the shorter one of the two electrical conductors by routing the added trace length entirely inside an area surrounded by a contact pad that electrically terminates the shorter one of the two electrical conductors. The routing for the differential pair with the added trace length is generated as output in the integrated circuit design.

Abstract: A method for integrating Six Sigma into an inspection receiving process of outsourced products may include the following steps: defining specification limits for product acceptance criteria; identifying and reporting a substandard product to authorized personnel for disposition via a MES (manufacturing execution system) and SCADA (supervisory control and data acquisition); preparing a report containing historical data, identifying root cause and assigning a corrective action; segregating the substandard product, and documenting the substandard product in the MES; disposing the substandard product; documenting and recording the corrective action in the MES; and outlining a method of recovery and eliminating a non-conforming incoming product. The present method may provide a device for a Closed Loop Corrective Action (CLCA).

Abstract: The present invention provides a method and a system of generic implementation of sharing test pins with I/O cells. The method includes a step of making a general change in a testlib file. The testlib file is suitable for controlling I/O cell pins to gain test access. The general change restricts I/O cells for sharing with test pins. The method further includes a step of making iogen changes for sharing. Optionally, the method may include a step of making a cell level change in the testlib file. The cell level change overrides restrictions defined by the general change.

Abstract: A method and computer program product for optimizing critical path delay in an integrated circuit design include steps of: (a) receiving as input an integrated circuit design; (b) performing a timing/crosstalk analysis to identify each timing critical net in the integrated circuit design; (c) selecting an optimum interconnect configuration for minimizing path delay in each timing critical net; (e) performing a detailed routing that includes the selected optimum interconnect configuration for each timing critical net; and (f) generating as output the detailed routing.

Abstract: The present invention is directed to a FIFO memory with single port memory modules that may allow simultaneous read and write operations. In an exemplary aspect of the present invention, a method for employing a FIFO memory with single port memory modules of half capacity to perform simultaneous read and write operations includes the following steps: (a) providing a first single port memory module for an even address of a read or write operation; (b) providing a second single port memory module for an odd address of a read or write operation; (c) alternating even address and odd address; and (d) when both a read request and a write request reach either the first single port memory module or the second single port memory module at a clock cycle, fulfilling the read request at the current clock cycle and fulfilling the write request at the next clock cycle.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: The present invention discloses a system for adjusting the speed of operation of a channel for communicating with disk drives in a multi ported system, comprising a bridge controller having a first channel and a second channel and a plurality of enclosure services modules, each having a first channel connected in sequence from a bridge controller to a first enclosure services module and successively connected to successive enclosure services modules to a last enclosure services module and each having a second channel connected in reverse sequence from the bridge controller to the last enclosure services module and successively connected to the successive enclosure services modules to the first enclosure services module.

Abstract: A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; calculating a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided; and calculating a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided.

Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.

Abstract: Methods and structure for improved tolerance of errors during initialization of a storage volume. More specifically, features and aspects of the invention provide for tolerating read errors during read-modify-write or read-peer-write processing of I/O requests overlapped with initialization of the volume affected by the I/O request. Features and aspects of the system detect such an error and, if the volume is being initialized, attempt graceful recovery of the error rather than shutting down or otherwise disabling the uninitialized volume.

Abstract: A method and computer program are disclosed for floorplanning and cell placement of an integrated circuit architecture that include steps of: (a) receiving as input a design for an integrated circuit architecture that includes a plurality of modules and an internal I/O ring; (b) creating a floorplan to define an area for placing module cells for each module in the plurality of modules wherein for each module that overlaps the internal I/O ring, an area of intersection between the area defined for placing the module cells and an area bounded by a side of the internal I/O ring for which the area of intersection is least is a global minimum for the plurality of modules; and (c) generating as output the floorplan for the integrated circuit architecture.

Abstract: A data bus transfers data between at least one slave device and a plurality of master devices, and an arbiter grants access to each of the master devices. The slave device includes look-ahead apparatus that includes staging register for staging an identification of a master device and a decoder for comparing a staged identification to an identification of a command from the bus. The look-ahead apparatus issues split releases of a next master device while the slave device returns data associated with a prior command.

Abstract: A method of manufacturing, e.g., integrated circuits, and of managing a manufacturing process. Product unit (circuit) variation data is collected from clustered product units (wafer sites). Collected data is grouped according to a selected manufacturing parameter. Each group is normalized for the selected manufacturing parameter. Normalized groups are combined. Normalized process data is checked for variances and the data is regrouped and renormalized until variances are no longer found. Each identified variance is correlated with a likely source. Then, each said likely source is addressed, e.g., a tool is adjusted or replaced, to minimize variances.

Abstract: Generating a density abstraction view for an integrated circuit design by dividing each block in the design that is larger than a predetermined size into a grid of rectangles; calculating a sum of metal area in each rectangle in the grid; creating an object in each rectangle having an area equal to the metal area sum of the rectangle; and storing all the created objects for the block as a view. The view may be stored in a layout database along with any other views for the integrated circuit design, and then used to determine density of a tile overlapping with the block by adding the area of the square objects in the density view that overlap with the tile to the tile.