Abstract: A system for estimating stage delay in an integrated circuit design includes steps of receiving as input an integrated circuit design including a single stage having at least two inputs, an output, and an interconnect connected to the output; calculating a separate interconnect delay for the interconnect as a function of an input ramptime for each of the inputs; adding a gate delay of each of the inputs to the separate interconnect delay calculated as a function of the input ramptime to estimate a stage delay for each of the inputs; and generating as output the stage delay for each of the inputs.

Abstract: An apparatus comprising a plurality of input cells, two or more local tie up cells, and two or more local tie down cells. The plurality of input cells may be configured to provide (i) one or more gate voltage signals and (ii) one or more supply voltage signals. The two or more local tie up cells may be configured to provide electrostatic discharge (ESD) protection to one or more first standard cells. Each of the local tie up cells may be coupled to (i) the one or more first standard cells and (ii) each of the gate voltage signals. The two or more local tie down cells may be configured to provide ESD protection to one or more second standard cells. Each of the local tie down cells may be coupled to (i) the one or more second standard cells and (ii) each of the supply voltage signals.

Abstract: A method for calculating frequency-dependent impedance in an integrated circuit (IC) having transistors coupled together by a line follows. First, partition the line into a plurality of rectangles of constant material. Then, solve for the minimum dissipated power in the plurality of rectangles. Finally, determine the frequency-dependent impedance from the minimum dissipated power.

Abstract: A library cell, a method and/or a system for adding the cell to a circuit is disclosed. The method generally comprises a first step for generating a final layout of the cell having an area of interest in at least one upper layer within a first layer stack used for the circuit, the first layer stack including at most all of a plurality of physical layers available for fabrication. A second step may include placing the final layout in the circuit. A third step may route a network of the circuit through the cell using the at least one upper layer and avoiding the area of interest according to at least one of a plurality of rules.

Abstract: Methods and structures for managing connection requests within a SAS controller operating as an initiator device. A SAS initiator device maintains a table of information regarding known SAS devices in the SAS domain. An index value is used by each of a plurality of link layer processing elements in the SAS controller to access information in the table. The index value is fewer bits than the complete eight byte SAS address and the logic to manipulate and compare the index value is therefore simpler than that required to directly manipulate a full SAS address. Further, the information table is shared by each of the link layer processing elements to further reduce complexity from replication of circuits and logic in the SAS controller.

Abstract: System, apparatus and method for controlling the movement of data in a data processing system. The apparatus receives commands from at least one protocol engine and generates contexts representing the commands. The contexts are a data structure representing information for programming data transfers pursuant to the commands. Instruction requests based on the contexts are issued to the at least one protocol engine and to at least one DMA to efficiently control the movement of data to/from the at least one protocol engine from/to a local memory. The functions within the system are partitioned in a way that allows functions to be scaled for better performance and/or to support different protocols.

Abstract: An apparatus includes a register of an integrated circuit for shifting a scan test pattern in response to a scan enable signal. The register includes: a shift input for receiving the scan test pattern; a system logic input for receiving a system logic signal; a clock input for receiving a next clock pulse; a scan enable input for switching the register between a shift mode and a normal mode; a register output for latching the shift input in the shift mode or the system logic input in the normal mode in response to the next clock pulse; and a scan enable gating circuit coupled to the scan enable input for holding the register in the shift mode while the scan enable signal is in the shift mode and immediately following a transition of the scan enable signal from the shift mode to the normal mode until after the register output has latched the shift input in response to the next clock pulse following the transition of the scan enable signal to the normal mode.

Abstract: A method and apparatus cancel repeatable run-out (RRO) errors in positioning on a recording medium using a RRO cancellation control voltage. The RRO cancellation includes (a) estimating a rotation period of the recording medium, (b) determining an update interval for the RRO cancellation control voltage based on the estimated rotation period and a desired number of updates to be performed per rotation, (c) updating a value of the RRO cancellation control voltage if a time period passed from a last update is greater than the update interval, and (d) applying the updated RRO cancellation voltage to control the positioning. A phase and a magnitude of the RRO cancellation control voltage may be determined for a RRO frequency range.

Abstract: A method for realization of an integrated circuit design including the steps of (i) receiving one or more design platform descriptions and (ii) merging the one or more design platform descriptions into one or more layers of a design flow. The one or more design platform descriptions provide design information about one or more platforms capable of instantiating the integrated circuit design.

Abstract: A hardware scheduler for a grooming switch with at least three switching stages accumulates a list of connection requests that cannot be granted given currently granted connection assignments. At a designated time, two data structures are dynamically built: an xRAM which records, for each output of a switch slice, which input is currently assigned to that output; and a yRAM which records, for each of the same outputs, the output of a second switch slice that is connected to a corresponding input of the second switch slice. Connections are assigned to satisfy the stored unassigned requests, by reassigning existing connection assignments using the xRAM and yRAM data structures.

Abstract: An apparatus comprising a processor, an interface circuit and a memory. The processor may be configured to operate at a first data rate in response to a first clock signal. The interface circuit may be configured to (i) operate in response to the first clock signal, and (ii) convert data received from the processor over a system bus from the first data rate to a second data rate. The memory may be (i) coupled to the interface circuit and (ii) configured to present/receive data to/from the system bus at the second data rate.

Abstract: A method of operating a circuit, comprising the steps of (A) buffering a read signal received within a plurality of first transfers to the circuit, (B) transmitting the read signal in a second transfer from the circuit, (C) buffering a first write signal received in a third transfer to the circuit and (D) transmitting the first write signal within a plurality of fourth transfers from the circuit.

Abstract: A method and apparatus for managing a plurality of change orders for a circuit design is disclosed. The method generally includes the steps of (A) receiving the change orders generated manually by a user, (B) analyzing the circuit design with all of the change orders implemented and (C) generating a report suitable for the user to understand based on a result of the analyzing.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for a Serial ATA interface that utilizes a combination of IOP control and specialized hardware control. The method may include steps as follows. It is determined, preferably based on a value of the Automate bit in a Task File Ram of a Serial ATA interface, whether a Serial ATA device of the Serial ATA interface is being controlled via the IOP or controlled by the specialized Serial ATA automation hardware. When the Serial ATA device is controlled via the IOP, the IOP may decide when to power up/down the Serial ATA interface. When the Serial ATA device is controlled by the specialized Serial ATA automation hardware, the method may proceed as follows. An idle or active condition of a Serial ATA interface utilizing a combination of IOP control and specialized hardware control is then automatically detected.

Abstract: The present invention provides an architecture of a memory Built-In Self Repair (BISR) controller for connecting to N memory instances, where N is a positive integer greater than 1. The architecture includes N groups of data ports, N BISR_SUBMOD modules for connecting to the N memory instances, and a CLK_IN input port and a BISR_IN input port for setting configuration of the memory BISR controller. Each of the N groups of data ports includes (1) a PHY_IN output port for connecting to input of a corresponding memory instance; (2) a PHY_OUT input port for connecting to output of the corresponding memory instance; (3) a LOG_IN input port for sending signals to the corresponding memory instance; and (4) a LOG_OUT output port for receiving signals from the corresponding memory instance. Each of the N BISR_SUBMOD modules includes a flip-flop, a first mux and a second mux. The CLK_IN input port is connected to clock inputs of all N flip-flops of the memory BISR controller.

Abstract: A method for creating a logic circuit with an optimized number of AND/OR switches, which evaluates a logic function defined in a high-level description. Through analyzing the dependency relationship among operators used to define the logic function, the present invention may simplify the functional steps used in the high-level description to define the logic function and thus create a logic circuit with an optimized number of AND/OR switches.

Abstract: A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.

Abstract: The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines, with each point representing a MUXed flip-flop holding a value, each line representing a checksum, and each set of parallel lines representing scan chains. The checksums for the flip-flops are calculated along a direction.

Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.

Abstract: A method for improving rate distortion performance of a compression system through parallel coefficient cancellation in a transform comprising the steps of (A) determining a block sum of absolute values for each of a plurality of blocks in a macroblock and (B) setting one or more coefficient values of a block to zero in response to a block sum value of said block being less than a first predetermined threshold value.