Abstract: A power-on reset circuit is provided, which includes a ground input, a power input having a voltage relative to the ground input, a reset output, a self-initializing latch, a high voltage trigger circuit and a discharge circuit. The self-initializing latch has first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input. One of the first and second latch nodes is coupled to the reset output. The high voltage trigger circuit is coupled to the first latch node and reverses the states of the first and second latch nodes when the voltage rises above a high trigger voltage. The discharge circuit is coupled to the second latch node and has a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage.

Abstract: An integrated circuit includes built-in self test (BIST) and built-in self repair (BISR) circuitry, a fuse array capable of storing information related to defective memory locations identified during the manufacturing process. During manufacture, the integrity of the embedded memory of the integrated circuit is tested under a variety of operating conditions via the BIST/BISR circuitry. The repair solutions derived from these tests are stored and compiled in automated test equipment. If the repair solutions indicate that the embedded memory is repairable, the on-chip fuse array of the integrated circuit is programmed with information indicative of all of the detected defective memory locations. The built-in self repair circuitry of the integrated circuit is not executed upon power up. Instead, the repair information stored in the fuse array is provided to address remap circuitry within the BISR circuit.

Abstract: A polishing pad for use in chemical mechanical polishing of a semiconductor substrate is described. The polishing pad comprises a substantially flat disk having a polishing surface for contacting the substrate. The polishing surface, which has a central region and a peripheral region, is segmented by a set of substantially parallel linear grooves. The grooves include central grooves which traverse the central region of the polishing surface, and peripheral grooves which traverse the peripheral region of the polishing surface. The central grooves have central groove dimensions, including a central groove width and pitch. The peripheral grooves have peripheral groove dimensions, including a peripheral groove width and pitch. At least one of the central groove dimensions, i.e. the width or the pitch, is different from the corresponding peripheral groove dimension.

Abstract: The present invention provides a method of forming a dielectric on a semiconductor substrate. A dielectric is grown at a substrate interface in a plurality of increments. Stress is relieved at the dielectric substrate interface between each increment. In another aspect, stress relief is performed by annealing the substrate. The annealing is performed by placing the substrate in an inert environment and by raising the temperature surrounding the substrate.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: A method of forming an electrically conductive via that abuts a key hole formed in filler material. A void is etched through the filler material in which the key hole is formed, thereby forming a link between the void and the key hole. A liner is formed within the void, where the liner is formed to a thickness that is at least about half a minimum cross sectional dimension of the key hole, so as to plug the link between the void and the key hole and thereby trap any contaminants within the key hole. Electrically conductive via material is deposited within the void to form the via.

Abstract: A method for identifying an integrated circuit having a latent defect. Test data corresponding to a set of integrated circuits is obtained, where the set of integrated circuits was processed on a single substrate. A subject integrated circuit is selected for analysis from within the set. A subset of integrated circuits is identified from within the set, where the subset includes integrated circuits that were located in close proximity on the substrate to the subject integrated circuit. The test data for the subset is analyzed to determine a defect parameter for the subset. The defect parameter for the subset is compared to a threshold. The subject integrated circuit is classified as having a latent defect when the defect parameter for the subset violates the threshold, and the subject integrated circuit is classified as not having a latent defect when the defect parameter for the subset does not violate the threshold.

Abstract: An on-chip apparatus and method for measuring signal skew between two on-chip signals are provided. The apparatus and method generate a pulse train which is at a first state during a time period between a clocking of a circuit component and a time at which the circuit component generates an output signal, and a second state between clockings of the circuit component. The pulse width of the pulses in the pulse train is representative of the skew, i.e. change of phases or timing, in the signal due to the presence of the component. The pulse train may further be pseudo-clock divided to generate more measurable pulses. The output from is produced using a single output pad. The apparatus and method produce a long measurable pulse width on a single output pad. A pulse width of 10 s of ns is achievable instead of 1-2 ns as in the known art. The pulse width measurement is done with a single tester channel instead of two as in the known art.

Abstract: A method and apparatus for managing transmission of data signals in a plurality of data lines. Data signals are received on the data lines and a reference signal. On each of the data lines, a delay between the data signal and the reference signal is measured to form a plurality of delay measurements. A set of delay values from the delay measurements is generated. In a preferred embodiment of the present invention, the delay values are selected to equalize the delay in each of the data lines to have the same delay as the data line having the longest delay. The delay values are used to adjust delay in a transmission in each of the plurality of data signals in the data lines. In the preferred embodiment of the present invention, the reference signal is set such that transitions for the data signals are centered to the middle of a pulse for the reference signal.

Abstract: Methods and associated structure for realignment of returned read data from the memory component to the memory controller to adjust for phase shift in the memory device's supplied strobe signals due to propagation delays and other layout, fabrication and environmental factors. The realignment features of the present invention impose a calibrated delay on the memory controller's clock signal used to sample registered read data from the memory components. By so adjusting the alignment of returned read data with respect to the memory controller's clock, the present invention obviates the need for an asynchronous FIFO as is presently commonly practiced in the art to avoid such phase shifts between memory components and associated memory controller's.

Abstract: A circuit comprising a processor and a translation circuit. The processor may be configured to present a first address. The translation circuit may be configured to (i) determine a mask and an offset, (ii) mask the first address to produce a first masked address, (iii) mask a second address to produce a second masked address, (iv) compare the first masked address with the second masked address, and (v) add the offset to the first address to present a third address in response to the first masked address being at least as great as the second masked address.

Abstract: A dual plasma process generates a microwave neutral plasma remote from a semiconductor wafer and a radio frequency (RF) ionized plasma adjacent to the wafer for simultaneous application to the wafer. A first gas flows through a microwave plasma generation area, without a second gas in the gas flow, to generate the neutral microwave plasma. The second gas is added to the gas flow downstream of the microwave plasma generation area prior to an RF plasma generation area.

Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: An air filtration system uses a liquid to remove impurities from the air. A specialized chamber allows the air and liquid to contact each other in close proximity, so that the liquid can pick up not only particulate matter, but fumes and toxic gasses as well. The air can be bubbled through the liquid, or the liquid can be introduced into the chamber as a gentle rain, a spray, a vapor, a waterfall, or any other configuration that allows active contact between the two mediums. The liquid can then be cleaned of contaminants, e.g., by centrifugal force, while the liquid is then reused.

Abstract: An equalization receiver responds to two differentially-related digital input signals occurring at a predetermined communication frequency. First and second input devices respond to the input signals and supply drive signals of a magnitude amplified relative to input signal by a factor related to the current conducted by the input devices. First and second current separate sources are connected to conduct current through the first and second input devices. An equalization circuit is connected between the first and second current sources. The equalization circuit has a frequency dependent impedance characteristic which exhibits a minimum impedance and a maximum coupling of the first and second current sources for the greatest current conductivity and the greatest amplification at the predetermined frequency.

Abstract: A pre-placement delay model for a logical function block of an integrated circuit design includes a fan-in count variable, a fan-out count variable and a delay variable. The fan-in count variable has a value indicative of a number of inputs to the logical function block. The fan-out count variable has a value indicative of the number of inputs of other logical function blocks that are driven by an output of the logical function block. The delay variable has a value that is a function of the binary logarithm of the fan-in count variable and the binary logarithm of the fan-out count variable.

Abstract: A cache may comprise a memory and control logic. The memory may be configured for storing data buffered by the cache. The control logic may be configured controlling accesses to the memory. The control logic may comprise a pseudo-noise generator and a trigger device. The pseudo-noise generator may be configured for generating a pseudo-random number representing, for a miss access requiring allocation, which of a plurality of possible addresses in the memory to use for the allocation. The trigger device may be configured for controlling a cycle of the pseudo-noise generator to output the pseudo-random number therefrom.

Abstract: Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. The electrical interconnection includes a semiconductor substrate having a conductive pad layer formed thereon. A dielectric layer having a plurality of elongate trenches is formed over the conductive pad layer such that the elongate trenches extend through the dielectric layer to the underlying conductive pad layer. Elongate conductive contacts are formed in the elongate trenches to establish electrical connections to the underlying conductive pad layer. The long axes of the elongate bar trenches can be arranged substantially parallel to the long axes of the slots formed in the copper pad. Alternatively, the long axes of the bar trenches can be arranged transversely to the long axes of the slots formed in the copper pad. In some embodiments, the conductive contacts are formed such that they establish electrical connection with sidewalls of the underlying conductive pad layer.

Abstract: A self-time circuit and method are presented for reducing the write cycle time in a semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method permits write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.

Abstract: An amplifier circuit includes a first input device coupled to a first input node and controlling a first current, a second input device coupled to a second input node and controlling a second current, a current source device coupled to a bias node and controlling a summed current of the first and second currents, a current mirror circuit, a first feedback circuit, a second feedback circuit, and a capacitor. The current mirror circuit generates a load current by mirroring the first current so as to provide an output signal voltage to an output node couple to the second output node. The first feedback circuit supplies a mirrored first current to the bias node, and the second feedback circuit pulls a mirrored second current from the bias node. The capacitor is coupled to the bias node and provides the bias voltage to the current source device.