Abstract: A method for generating one or more hardmacro technology files comprising the steps of determining a netlist, generating a timing constraints file in response to (i) the netlist and (ii) a time budget, and generating the hardmacro technology files in response to (i) the netlist and (ii) the timing constraints file.

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A method for inserting and reading probe points in a silicon embedded testbench comprising the steps of (a) reading a simulation list of probe points, (b) enabling access to the list of probe points, (c) generating a core, and (d) displaying or comparing the probe points.

Abstract: Data transfers from the peripheral interface of a disk array to a data buffer are snooped to determine if the starting address of a data transfer matches an entry in a list of starting addresses for requested data. If a match is identified, third party transfer is initiated and the data is simultaneously transferred to the host interface of the host system. The resulting data bandwidth is increased. A throttling/suspension mechanism can temporarily or indefinitely hold up actual data movement into the data buffer to allow for temporary buffering and interface speed matching as data is transferred to the host interface.

Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.

Abstract: A clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. When the tree deskew circuit is deskewed for a multilevel clock tree, the temporary clock net of that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals.

Abstract: An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.

Abstract: A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.

Abstract: A heat spreader for use with an integrated circuit in a package, where the heat spreader is formed as a plate having a centrally disposed aperture with a diameter that is smaller than a minimum diameter of the integrated circuit. The heat spreader has an overall diameter that is no greater than a minimum diameter of the package. In this manner, the aperture in the heat spreader allows the plastic injected through a top gated mold form to pass through the heat spreader and more uniformly encapsulate the integrated circuit.

Abstract: A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers of identical sub-modules. The scalable modules are not part of the functional circuitry of the IC, but the spare gates within their sub-modules may be incorporated into faulty functional circuitry to correct the logic error. This is accomplished by altering the metalization layer of the IC to reconnect the spare gates, and does not require changing the physical layout (i.e., adding more pins, relocating gates, etc.) of the IC.

Abstract: An active heat sink uses a liquid coolant to transfer heat from a hot zone to a cool zone. The liquid coolant is propelled using a motor comprised of a plurality of external coils that are in magnetic communication with a plurality of magnets attached to a pump gear. The motor does not require any penetration of the liquid cavity. Further, the heat pump may have a temperature monitoring circuit to determine whether or not the pump should be activated.

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom.

Abstract: An integrated process tool monitoring system for semiconductor fabrication. Specifically, a process tool parameter auditing system, where a process tool user need not run a different verification system for each process tool type used and need not download parameters every time before a semiconductor device or material is to be processed by the process tool.

Abstract: A method and apparatus for processing data packets through direct memory access (DMA) in transferring data packets between a bus and an apparatus containing DMA engines. The DMA engines process different contexts, also referred to as distinct logical data streams. The phase of a bus along with the status of DMA transactions are monitored. The phase and the status are used to dynamically allocate priorities to the DMA engines to maximize the efficiency in processing data.

Abstract: A change, such as an ECO, is transformed to a gate-level netlist. The change is incorporated in cells of a synthesizable source design. A domain is defined in the netlist that contains cells that are equivalent to the cells of the source design that incorporate the change. The cells of the synthesizable source design that incorporate the change are substituted for the domain in the netlist. The substituted synthesizable source design domain is resynthesized into the gate-level netlist that includes the change.

Abstract: A computer system operating system (OS) is booted from a storage media formed from a redundant array of independent disks (RAID). An interface adapter is connected to a system bus, and the interface adapter includes a nonvolatile option ROM memory which has RAID I/O algorithmic instructions recorded therein. When a basic input output system (BIOS) is executed during booting, a BIOS hardware detect instruction set of the BIOS scans the system bus and causes the RAID I/O algorithmic instructions to be read from the option ROM memory for use by a BIOS I/O instruction set, and the BIOS I/O instruction set uses the RAID I/O algorithmic instructions obtained from the option ROM memory to read the OS from the RAID storage media.

Abstract: The present invention may relate to a digital to analog converter for converting a digital signal to an analog signal. The digital to analog converter may comprise decoder logic, an array of clocked sub-circuits, a clock generator and a clock signal controller. The decoder logic may be configured to decode the digital signal to a plurality of control signals for controlling generation of the analog signal. The array of clocked sub-circuits may be configured to receive the control signals. The clock generator may be configured to generate a clock signal for clocking the sub-circuits. The clock signal controller may be configured to inhibit application of the clock signal to one or more of the sub-circuits.