Abstract: A method of testing an integrated circuit. A first subset of test parameters is selected from a full set of test parameters designed to characterize given properties of the integrated circuit. A first subset of devices in the integrated circuit is tested with the first subset of test parameters, using different input levels to determine an acceptable low input level and an acceptable high input level for the first subset of test parameters on the first subset of devices. At least a second subset of devices in the integrated circuit is tested, where the second subset of devices is greater in number than the first subset of devices. The test is accomplished with at least a second subset of test parameters using the acceptable low input level and the acceptable high input level, to determine whether the integrated circuit functions properly at the acceptable low input level and the acceptable high input level.

Abstract: An integrated circuit with a VDDio bus line disposed on a first layer of the integrated circuit. The VDDio bus line is disposed along a length, and has a first width transverse to the length. A VSSio bus line is dispose on a second layer of the integrated circuit. The VSSio bus line is disposed along the length and has a second width transverse to the length. The second width of the VSSio bus line substantially overlaps the first width of the VDDio bus line. An input output cell is disposed on a third layer of the integrated circuit. The first layer, the second layer, and the third layer are all different layers of the integrated circuit. The input output cell has a first transistor electrically connected to the VDDio bus line, and a second transistor electrically connected to the VSSio bus line. The first transistor and the second transistor are disposed along the length within the input output cell.

Abstract: An integrated circuit input buffer is provided, which includes a differential buffer, first and second average value circuits and a feedback amplifier. The input buffer is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.

Abstract: The present invention is directed to a method and system for expanding volume capacity. A method of expanding volume capacity on a storage device may include receiving a request to expand capacity of a target volume by a requested amount. A first hierarchy is queried for unused capacity, wherein if unused capacity is at least one of greater than or equal to the requested amount, the unused capacity is positioned within the target volume. If unused capacity is less than the requested amount, at least one successive hierarchy is queried to locate unused capacity, which is at least one of greater than or equal to the requested amount, the successive hierarchy located at a logic block address further from a target volume logic block address than a first hierarchy logic block address. The unused capacity is then positioned to be included with the target volume.

Abstract: A multiport BIST method and apparatus therefor are disclosed. The multiport BIST is advantageously based on adapting a single port BIST method by dividing the memory into sections based on the number of ports and applying the single port BIST simultaneously through all ports simultaneously (inverting where appropriate), so as to test the sections in parallel. In one embodiment of the invention, an integrated circuit device comprises a multiport memory and a built-in self-test (BIST) unit that applies a first test pattern of read and write operations to a first port of the memory and applies a second test pattern of read and write operations to a second port of the memory. The addresses in the first test pattern are offset from addresses in the second test pattern by a fixed amount. The ports preferably have adjacent bit lines, and the data values conveyed by the first and second test patterns are preferably complementary.

Abstract: The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where a single one of the heat spreaders is associated with a single one of the integrated circuits, but not all of the integrated circuits have an associated heat spreader. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: A long channel transistor and a shorter channel transistor operate in conjunction to drive an output node. The long channel device is first activated by a drive signal and the drive signal is input to a delay element that then activates the shorter channel device. By enabling the long channel device first, hot carrier injection effects are reduced. Employing two transistors that are sized to operate in different voltage ranges reduces surge current. The two-transistor configuration of the present invention occupies less area than a single long channel device with similar drive capabilities.

Abstract: A bonding pad for an integrated circuit, having a conductive base layer. The conductive base layer has slots formed in it, where the slots extend completely through the conductive base layer. An insulating layer is disposed on top of the conductive base layer. The insulating layer protrudes into the slots of the conductive base layer. The insulating layer also includes a low k material. A conductive top layer is disposed on top of the insulating layer.

Abstract: A method for forming shallow junctions in a substrate. The substrate is masked with a first mask to selectively cover first portions of the substrate and selectively expose second portions of the substrate. A first dopant is implanted substantially within a first depth zone through the second portions of the substrate. The first depth zone extends from a first depth to a second depth, and the first depth is shallower than the second depth. The substrate is annealed for a first time to form a noncontiguous buried insulating layer substantially within the first depth zone in the second portions of the substrate. The substrate is masked with a second mask to selectively cover third portions of the substrate and selectively expose fourth portions of the substrate. The fourth portions of the substrate at least partially overlap the second portions of the substrate. A second dopant is implanted substantially within a second depth zone through the fourth portions of the substrate.

Abstract: Methods of operation and systems for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide a register interface and associated processing capabilities to simplify firmware processing to save and restore context information regarding block transfer operations that are paused and resumed prior to completion. Furthermore, the invention provides for architecture and associated methods for processing of standard scatter/gather list elements by a standardized scatter/gather list processor embedded within DMACs and IOPs. Specifically, as applied in the context of SCSI or Fibre Channel IOPs, the scatter/gather list processor of the present invention simplifies IOP firmware processing to save the current block transfer context on occurrence of a SCSI disconnect and to restore the saved context on occurrence of a SCSI reselect.

Abstract: An automatic delay matching circuit for a data serializer includes a phase-locked loop for synthesizing a transmitter clock signal for an external circuit, a phase interpolator coupled to the phase-locked loop for delaying or advancing the transmitter clock signal in response to a phase control signal to generate a delayed or advanced transmitter clock signal for the data serializer, a phase detector for measuring a phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through an external circuit, and a loop filter coupled to the phase detector for generating the phase control signal as a function of the phase difference between the delayed or advanced transmitter clock signal further delayed through the data serializer and the transmitter clock signal delayed through the external circuit.

Abstract: Provided is an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal is connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal include at least one bit based solely on a corresponding bit in the quantity and at least one bit based solely on a value of the increment/decrement signal.

Abstract: A multipurpose configurable bus independent simulation bus functional model for testing a circuit is described. The multipurpose bus functional model utilizes a configurable data structure to interact with a device being tested by providing high-level test generation routines defined by the bus interface specified. The configurable data structure allows for verification of both signal timing and functional operation bus specifications. This data structure technique utilizes a standardized and parameterized method that allows variations and multiple instances of test bench models to be generated and instantiated in a design test environment. The bus functional model also sub-divides general functions and data structures into separate re-usable functional blocks. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure.

Abstract: Block-level storage is managed in a computerized storage system by recording into a write-ahead log a description of block-level updates made to data in a volume in a main memory and in a storage device of the computerized storage system. The write-ahead logging enables directory updates for each block-level write request to be logged, so the write request can be allowed to complete independently of other write requests.

Abstract: The present invention is directed to a system and method for reading and writing N-way mirrored storage devices. A method of reading data in a data storage system, where the data storage system may include a first data storage device, a second data storage device and a third data storage device, is provided. A first item of data is read from a first data storage device, a second item of data is read from a second data storage device, and a third item of data is read from a third storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device and the third item of data from the third storage device. If the first item of data matches at least one of the second item of data and the third item of data, the first item of data is valid. If the first item of data does not match at least one of the second item of data and the third item of data, the second item of data is valid.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.

Abstract: A wire bond package for an integrated circuit die includes a first I/O core ring and a second I/O core ring formed in a first metal layer; a pad strap formed in a second metal layer overlapping the second I/O core ring; a via formed between the first metal layer and the second metal layer where the second I/O core ring and the pad strap overlap; a first core ring formed in a third metal layer overlapping the first I/O core ring; a via formed between the first metal layer and the third metal layer where the first I/O core ring and the first core ring overlap outside the power strap; a first power mesh formed in a fourth metal layer overlapping the first core ring; and a via formed between the third metal layer and the fourth metal layer where the first core ring and the first power mesh overlap.

Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.