Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.

Abstract: A system and method are presented for incorporating boundary scan test capability in an embedded memory. Existing half-latches within the memory are augmented to create full-latches, configurable as a scan register. This requires substantially less circuitry than if the entire scan register was created separately. Furthermore, separate signal paths are maintained for the functional signals and for the boundary scan data. Therefore, the boundary scan logic does not contribute additional propagation delay to the functional signals. Also, because the test circuitry is within the memory (rather than external to it), placing and routing of the scan circuitry is much less complicated than with previous methods.

Abstract: A capacitor has a pair of plates separated by a capacitor dielectric material which is formed of multiple separate layers of different dielectric materials having different electrical characteristics. The different electrical characteristics are represented by linearity curves that curve relatively oppositely with respect to one another. Combining the different dielectric materials and separate layers achieves selected electrical characteristics from the overall capacitor dielectric material. The capacitor dielectric material may be formed with a top layer, a middle layer and a bottom layer. The middle layer may be formed of relatively high leakage dielectric and/or relatively high dielectric constant material, and the top and bottom layers may be formed of barrier material which is substantially resistant to leakage current and which exhibits a relatively lower dielectric constant.

Abstract: Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge.

Abstract: An optical-disk play-back system has a lens that receives a light beam reflected from a data surface of an optical disk. The lens focuses the light on four quadrant photodiodes. The position of the lens relative to the photodiodes is adjusted by a standard tracking control loop. In addition, the sledge position is controlled by a sledge-center-error signal. Since the sledge position changes only infrequently, the center error is a low-frequency signal. A non-linear center-error-generating circuit uses two op-amp stages. Signals from an inner pair of photodiodes are summed and applied to one input of the first-stage op amp, while signals from an outer pair of photodiodes are summed and applied to the other input of the first-stage op amp. The first-stage op amp output an overall error signal that includes high-frequency errors. A high-pass filter removes low-frequency components output from the first-stage op amp. The high-pass filter drives an inverting input of the second-stage op amp.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).

Abstract: A battery charging circuit for portable electronic devices including a photovoltaic cell for generating electrical current for charging of batteries. The charging circuit includes a state machine charge control circuit to selectively apply the electrical current generated by the photovoltaic cell to the batteries for charging and/or to the operational circuits of the portable electronic device for operation of the device. The photovoltaic cell, charge control circuit and operational circuits may be packaged in a number of alternative embodiments. In a first embodiment the photovoltaic cell and charge control circuit are integrated in a single circuit package. In a second, the various components are in separate circuit packages to enhance flexibility in design options. In a third embodiment, the charge control circuit is integrated with the operational circuits of the device.

Abstract: A method of analyzing ADCs, comprising providing a test waveform, sampling the test waveform in an ADC at a frequency different from the test waveform, providing the output samples of the ADC to a logic analyzer means, storing the output samples over a predetermined time interval in memory in the logic analyzer means, and providing from the stored samples, a graphical visual representation of the sampled test waveform.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: A graphical video editing system that allows manipulation of images for input to the video encoding and decoding process. The debugging of video encoders and decoders is aided by user controlled editing of problem areas in test images, and the graphical video editing system is coupled directly to the video encoder or decoder being debugged so that the effects of the editing can be immediately observed. This system advantageously provides a speedup in the debugging process by simplifying the detection of problem areas and providing a fast method for narrowing the possible causes of image flaws. Broadly speaking, the present invention contemplates a graphical video editing system for regeneration of bitstreams. The system comprises an encoder module, a decoder module, a display editor module and a display. The encoder module is configured to receive an input image and to convert the input image into an encoded bitstream.

Abstract: Water for use in wet oxidation of semiconductor surfaces may be generated by reacting ultra pure hydrogen and ultra pure gaseous oxygen without a flame. Because no flame is used, contamination due to a flame impinging on components of a “torch” is not a problem. Flame-free generation of water is accomplished by reacting hydrogen and oxygen under conditions that do not result in ignition. This may be accomplished by provided a diluted hydrogen stream in which molecular hydrogen is mixed with a diluent such as a noble gas or nitrogen. This use of diluted hydrogen also reduces or eliminates the danger of explosion. This can simplify the apparatus design by eliminating the need for complicated interlocks, flame detectors, etc.

Abstract: An apparatus performs motion estimation based on a reference image and a target image. The apparatus has a command memory for storing a motion estimation command list segment and a search engine connected to the command memory. The search engine retrieves and processes the command list segment stored in the memory. The search engine in turn has a reference window memory containing one or more reference data segments, a target memory containing one or more target data segments, and a data path engine for generating a score for each offset between data in the reference window memory and data stored in the target memory. A result memory receives outputs from the motion estimation search engine in the form of motion estimation result list segments. The reference window memory, target memory, and result memory may be double-buffered to minimize system memory latencies. Moreover, target and reference fetches may be shared by up to four search targets in a split search command.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.

Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.

Abstract: A method and apparatus for increasing performance in a data processing system. The data processing system includes a plurality of storage devices and a backup storage device. The backup storage device is configured as a log device. Data is logged to the backup storage device after the backup storage device has been configured as a log device. In response to a failure of a storage device within the plurality of storage devices, the backup storage device is reconfigured to be used as a replacement for the failed storage device.

Abstract: An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of interim devices. The invention provides a method in which additional portions or subsystems of the integrated circuit are incorporated into successive versions of the interim device. In this manner, the invention provides for the gradual incorporation of a plurality of architectural subsystems into the integrated device such that the synthesis and verification of each iteration is broken into manageable pieces. In the preferred embodiment, this design method is facilitated by incorporating a programmable portion into the design flow of each interim device such that each interim device includes a custom portion into which the subsystems that have been implemented in silicon are fabricated and a programmable portion.

Abstract: A multimedia decoder is provided that inserts synchronization words into elementary linear pulse-code modulation (LPCM) audio bitstreams. In one embodiment, the multimedia decoder includes a pre-parser, a memory, and an audio decoder module. The pre-parser receives a multimedia bitstream and separates it into an audio substream and a video substream, and inserts a synchronization words before each data packet in the audio substream while forming it into an elementary bitstream. The memory is coupled to the pre-parser to buffer the elementary audio bitstream, and the audio decoder module is coupled to the memory to retrieve the elementary audio bitstream and convert it into a digital audio signal. The inserted synchronization word may comprise between from four to ten bytes in length. In one particular implementation, the inserted synchronization word includes the ASCII representation of the letters LSILOGIC.

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.