Abstract: A support structure is provided between, preferably approximately midway between, a semiconductor die and the inner ends of the lead fingers of a lead frame. Intermediate portions of bond wires connecting the die to the lead fingers are bonded, or tacked, to an upper surface of the support structure. In this manner, the length of the bond wires can be doubled, and the lead fingers can be commensurately further from the die so that a greater number of lead fingers of a given size and spacing can be provided, while avoiding the problems associated with long bond wires.

Abstract: An ASIC device and method provide clock signals to load circuits having a balanced clock tree including a master clock line, for example a clock trunk or H-tree, and branched clock lines feeding the clock signals to load circuits and being balanced with respect to the delays and loads in domains of the ASIC device to which the branched clock lines supply the clock signals. The ASIC device and method generate derived clock signals by gating the master clock signal, in which the derived clock signals have a frequency reduced by a factor n>1 (n=2, . . . , N), which is adapted to the need of the load circuits in a particular domain, and route the master clock signal and/or the derived clock signal for a particular domain to the load circuit of said domain.

Abstract: A scripting tool for executing a script command having at least one parameter includes a display device, a processor, and a memory. The memory has stored therein instructions which when executed by the processor cause the processor to generate a user input control for a parameter of the script command based upon a definition file, and display the user input control upon the display device. The instructions of the memory when executed by the processor further cause the processor to receive user input via the user input control, and generate a parameter value based upon the user input. Moreover, the instructions when executed by the processor cause the processor to set the parameter of the script command equal to the parameter value, and execute the script command based upon the parameter.

Abstract: A method of using a frame sequence to transmit a data block from a transmitting device to a receiving device is disclosed. One step of the method includes generating a first frame of the frame sequence that includes a last portion of the data block and a relative offset which indicates a relative displacement between a first portion of the data block and the last portion of the data block. Another step of the method includes generating a second frame of the frame sequence that includes the first portion of the data block. The method also includes the step of transmitting the first frame of the frame sequence from the transmitting device to the receiving device before transmitting the second frame. Yet another step of the method includes receiving the first frame of the frame sequence from the transmitting device before receiving the second frame.

Abstract: A system and method for motion vector extraction and computation is embodied in an architecture adapted to overlap a data extraction process with a computation process and to provide 2-frame store decode with letterbox scaling capability, to extract a plurality of parameters usable for calculating a motion vector, and to compute motion vectors. The architecture is adapted to compute vertical and horizontal components of motion vectors in back-to-back cycles. The architecture includes a motion vector compute pipeline which, in a preferred embodiment includes a delta compute engine, a raw vector compute engine, a motion vector with respect to top left corner of picture block, or a combination of these logic circuits. The delta compute engine is adapted to generate a delta from a motion code and a motion residual and to compute a predicted motion vector in consideration of a motion vector of a previous macroblock.

Abstract: A system and method for fax transmission over a fax relay network that includes at least a wideband portion and a narrowband portion, includes a first fax relay gateway communicatively connecting a sending fax machine on the wideband portion of the network to the narrowband portion of the network, the first fax relay gateway receiving image data from the sending fax machine and outputting digitized image data in accordance with a data rate of the narrowband portion of the fax relay network. A second fax relay gateway, communicatively connects a receiving fax machine to the narrowband portion of the network. At least one of the first fax relay gateway or the second fax relay gateway includes a control process that determines whether an amount of data stored in a buffer in the fax relay gateway is greater or less than a particular threshold or determines that the amount of jitter in the narrow band network exceeds a particular threshold, and if so, initiates a retrain procedure to adjust the fax data rate.

Abstract: A method, system, and program for selectively testing output signals of an integrated circuit. The system comprising a mask generation file specifying output signals and test cycles and a verification module to check simulation output data and generate test pattern data. The verification module further comprising an extractor routine which receives the mask generation file and processes the simulation output data such that the test pattern data is coded to mask the specified output signals at the specified test cycles. The verification module further comprising margin analysis for determining if margin times of the coded test patterns fall below a minimum margin time setting.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output signal having a predetermined slew rate and propagation delay in response to a first input signal and a control signal. The second circuit may be configured to generate a second output signal having a predetermined slew rate and propagation delay in response to a second input signal and the control signal.

Abstract: Provided is an apparatus and method for modifying the manufacture of chip carrier bond pads to increase the quality and reliability of semiconductor packages and ball joints in particular. This is accomplished by minimizing the corrosion of the barrier metal layer on the functional bond pads during gold deposition with the use of sacrificial pads electrically connected with the functional bond pads. According to one embodiment of the invention, a semiconductor package has copper conductive pads on a substrate that are exposed through a dielectric. Both functional and sacrificial (nonfunctional) copper conductive pads are provided. A barrier metal layer composed of nickel is electrolessly plated onto these conductive pads, and a bond metal layer of gold is deposited onto the nickel using electroless, generally immersion, gold plating.

Abstract: A system and method upgrade an original data storage system into an enhanced data storage system. The original data storage system includes an original storage array controller device and an original storage array. The original data storage system is initially connected to a host system via a host bus and presents to the host system an original logical volume mapping associated with a logical identifier and mapped to a physical data set stored in individual storage devices in the original storage array. An enhanced storage array controller device is operatively connected to the host system via the host bus, and the original storage array controller device and a storage connection device coupled to another storage array are operatively connecting to the enhanced storage array controller device via an intermediate bus. The physical data set of the original storage array is redistributed across a plurality of storage arrays, including the original and the other storage arrays.

Abstract: Disclosed is an integrated circuit structure having one or more metal lines thereon with metal line sidewall retention structures formed on the sides of the metal lines. The metal line sidewall retention structures comprise a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line during subsequent processing or use of the metal line. The metal line sidewall retention structures are formed by anisotropically etching a layer of a material sufficiently hard to inhibit lateral distortion or expansion of portions of the metal line after formation of a layer of such a material over and around the sides of the metal lines.

Abstract: A method and apparatus for performing efficient reseeks in an optical storage device. As data sectors are read by the optical storage device, address information corresponding to sectors being processed by the optical storage device is stored in a stack. The stack may be composed of shift registers that shift the address information of new sectors down the stack as they are read. When an interrupt occurs, a selector determines which stack location contains address information for the sector being processed, and transfers the address information to a register. The address information is held in the register until it is accessed by a microprocessor. The microprocessor uses the address information to determine a reseek location, and causes the sector being processed to be read again.

Abstract: A detection circuit for receiving a pair of unstable input signals along a pair of input leads and providing a stable output signal along an output lead, preferably to downstream circuitry. The detection circuit includes a plurality of transistors including a first transistor and a second transistor, wherein at least one of the first and second transistors is configured to turn on upon the detection circuit receiving input signals along the pair of input leads. At least one of the first and second transistors is configured to provide a signal along a lead to circuitry which is configured to condition the output signal and turn on a third transistor. The third transistor is connected to the first and said second transistors such that when the third transistor turns on, the third transistor prevents the first and second transistors from turning on until a new clock signal is received by the detection circuit.

Abstract: A method of fabricating a semiconductor wafer having an active area and an inactive outer clear out area includes the step of fabricating a number of active dies on a first side of the wafer such that each of the number of active dies is completely contained within the active area of the wafer. The method also includes the step of generating a laser beam with a laser device. Moreover, the method includes the step of scribing a code in the inactive outer clear out area of the wafer with the laser beam such that the code is completely contained within the inactive outer clear out area of the wafer. An apparatus for scribing a code in an inactive outer clear out area of a first side of a semiconductor wafer is also disclosed.

Abstract: A low dielectric constant multiple carbon-containing silicon oxide dielectric material for an integrated circuit structure is described which comprises a silicon oxide material including silicon atoms which are each bonded to a multiple carbon-containing group consisting of carbon atoms and primary hydrogens. Preferably such multiple carbon-containing groups have the general formula —(C)y(CH3)z, where y is an integer from 1 to 4 for a branched alkyl group and from 3 to 5 for a cyclic alkyl group, and z is 2y+1 for a branched alkyl group and 2y−1 for a cyclic alkyl group.

Abstract: A delay cell, a method for generating a delay, and a differential ring oscillator are disclosed. The delay cell provides a stable delay with a low voltage power supply, and has a high power supply rejection ratio. The delay cell generally comprises a first and second input receiver on a first and second branch, respectively, to receive an input to control a current on each branch, each branch includes an output node capacitively coupled to a power supply. Each branch may include a current source coupled between the output node and the power supply and/or a lower limit clamp coupled between the output node and the power supply to maintain an output at the output node above a lower limit. The delay cell may also include a first and a second current diverter coupled to the first and second branch for diverting current on the first and second branch away from the first and second input receiver, respectively.

Abstract: A method and apparatus for receiving packets from a bus. A packet is received at an interface to the bus. The packet is parsed, and a determination is made whether to retain the packet from the parsing of the packet. The packet is placed in a buffer with a header. The packet is moved from the buffer to another bus using information located within the header, wherein repeated parsing of the packet to move the packet to another bus is unnecessary.

Abstract: A method for planning the clock distribution network in the conceptual design phase of an ASIC device is provided herein that comprises partitioning the technology-independent description of the device into partitioned groups based on the clocking time of the clock recipients in each of the partitioned groups. In addition, a clock budgeting plan is generated by creating target timing groups and assigning each of the partitioned groups to one of the target timing groups based on the clocking time of the clock recipients in each of the partitioned groups. The clock recipients in each of the target timing groups clock at a substantially same time and clock recipients in different target groups clock at different times.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: A host register interface testing system and method are disclosed. The system includes a host register unit including information that is indicative of a set of host registers corresponding to a programmable device under test. The system further includes a rule set unit including information that is indicative of constraints on values that the set of host registers may assume and a test setup generator configured to access the host register unit and the rule set unit and to generate a set of test setups based on the contents of the host register unit and the rule set unit where each test setup corresponds to a valid state of the set of host registers. In one embodiment, the test setup generator is suitable for applying a test setup from the set of test setups to the device under test. In one embodiment, the system may further include a verifier configured to receive the output of the device under test and, based thereon, for determining the functionality of the device under test.