Abstract: A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. A receiver of the transceiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port.

Abstract: An algorithm based on motion compensation uses a temporal support of five fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to complete the progressive video frame.

Abstract: A disk mirroring method operable in a disk array storage system for storing N images of a block of data across M drives (N>=3 and M>=N) to enhance flexibility in configuration of mirrored and non-mirrored LUNs. Each of the N copies of data resides on a different drive such that if N−1 drives fail, the original block of data is recoverable. Data blocks may be striped or non-striped over the plurality of drives. Where the data is striped, each segment of the stripe has at least two mirrored images on other drives of the array. The present invention therefore enhances configuration flexibility as compared to prior techniques because all drives of the array may be used for mirrored copies regardless of the number of drives. The present invention therefore does not waste space where, for example, an odd number of drives are configured in the LUN.

Abstract: A system for coupling a ball fitting connected to a first tubing to a socket fitting connected to a second tubing. A first coupling forms an aperture having a diameter that is larger than the diameter of the ball fitting, and receives the ball fitting. The first coupling forms an annular race, with an annular surface disposed between the annular race and the aperture. First split ring pieces are assembled into a first ring that forms an aperture having a diameter that is smaller than the diameter of the ball fitting, and receives the first tubing. The first ring forms an annular ridge that engages the annular race, and aligns the first split ring pieces. The annular surface applies uniform axial pressure to a first surface of the first ring. The first ring has a second surface opposing the first surface that applies uniform axial pressure to a back portion of the ball fitting.

Abstract: One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent.

Abstract: A method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout, and a wire bonded electrical interconnection formed using the method consists of the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.

Abstract: An apparatus for determining temperature of a semiconductor wafer during wafer fabrication is disclosed. The semiconductor wafer has a response circuit. The apparatus includes a signal transceiver for (i) transmitting an interrogation signal which excites the response circuit, and (ii) receiving a response signal generated by the response circuit. The apparatus also includes a processing unit electrically coupled to the signal transceiver. The apparatus also includes a memory device electrically coupled to the processing unit. The memory device has stored therein a plurality of instructions which, when executed by the processing unit, causes the processing unit to (a) operate the signal transceiver to (i) transmit the interrogation signal so as to excite the response circuit during fabrication of the semiconductor wafer, and (ii) measure the response signal generated by the response circuit, and (b) determine temperature of the semiconductor wafer based on the response signal of the response circuit.

Abstract: A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element.

Abstract: A power on reset cell is disclosed capable of accommodating faster power cycling rates and providing better trip point control. When the input supply voltage ramps up, the output of the power on reset cell transitions when the input is greater than a predetermined value. The power on reset cell includes a discharge circuit that is capable of discharging a subcircuit of the power on reset cell when the input supply voltage ramps down so that the output of the power on reset cell is prevented from prematurely transitioning during a subsequent ramping up of the input due to any latent charge accumulated in the prior ramping up cycle. The discharge circuit allows the power on reset cell to undergo faster power cycling without providing an invalid output. Furthermore, the discharge circuit provides better control of the output trip point.

Abstract: A bidirectional communications interface employs the same path for transmitting and receiving. The bidirectional communications interface includes one two winding transformer for both transmit and receive and an integrated circuit having a transmitter and a receiver each connected to the same pair of input/output pins. The interface enables a communications node in a communications network to transmit data to and receive data from other nodes in the network.

Abstract: A digital logic circuit, such as a FIFO memory includes pointers, or indicators, generated in two clock domains, between which information is transferred, to indicate a location in the digital logic circuit for transferring the information into or out of the digital logic circuit within either clock domain. Each pointer is encoded with a “2-hot” encoded value within one of the clock domains. The 2-hot encoded value of each pointer is sent to the other clock domain to synchronize the pointer to the other clock domain as well as to its original clock domain. Within each clock domain, the pointer generated therein and the pointer received from the other clock domain are used to determine whether the information can be transferred into or out of the digital logic circuit.

Abstract: Methods and systems for mapping logical disk addresses to physical locations so as to achieve consistent sustained performance for a striped disk array I/O subsystem. Stripes (regions) are defined by a region mapping table. Zones are defined by the disk manufacturer as groups of cylinders having identical number of sectors per track. Outer zones store more data and therefore provide a higher level of sustained performance as compared to inner zones. Substantially half the disks in the array are mapped such that logical sequential blocks are allocated from outer most, higher performance, zones to inner, lower performance, zones. The other half of the drives in the array are mapped from inner zones to outer zones. Each region (stripe) therefore includes a mix of higher performance zones and lower performance zones. Each region therefore provides more consistent sustained performance as compared to prior techniques.

Abstract: A memory architecture which includes a plurality of memory cells arranged in rows and columns. A word line is connected to each row of memory cells, and a plurality of bit lines are connected to each column of memory cells. Providing that more than one bit line is connected to each column of memory cells improves the performance of large memories, provides reduced access times without having to increase the size of the memory, and provides that a large memory consumes less power. The bit lines may each be formed of the same material, or they may be formed of different material depending on the application. The memory cells may be disposed in a plurality of arrays, and the arrays may be symmetrical (i.e. where each array is the same size) or asymmetrical (i.e. where the arrays are not the same size).

Abstract: Provided is a technique for reducing skew in routing a clock signal in an integrated circuit device by prerouting an H trunk, dividing the H trunk into parts, and balancing delays in one of the parts by adding snaking wire. In a more particular aspect, the clock signal is prerouted as an H trunk, and the H trunk is divided into a left-top quadrant, a left-bottom quadrant, a right-top quadrant, and a right-bottom quadrant. The signal delays are balanced as between the two left quadrants by adding snaking wire, the signal delays are balanced between the two right quadrants by adding snaking wire, and the signal delays are balanced between the right half and the left half by adding snaking wire.

Abstract: A method and apparatus for providing data backup in a computer system. Check information can be calculated and stored on a sequential arrangement of data drives such that the loss of a single data drive does not impair the reading or writing of information on that data drive. Should more than one data drive fail or several drives fail, data can still be resurrected by chaining back through the arrangement of drives to calculate lost information. An optimum number of drives can be determined when the known number of data drives and known number of check drives and known number of check drives associated with each data drive is known. Should a data drive fail, a system for re-establishing a new data drive out of the existing check drives can be implemented.

Abstract: A system and method to establish an end-to-end error correcting protocol between two voice band data modems over a network including voice band data relay gateways, where part of the end-to-end connection is via low data rate narrowband network. Using a partial implementation of V.42 LAPM protocol within the data relay gateways, the system allows the independent selection of modulation schemes at each gateway as well as increased user data throughput by removing non-informational data. Flow control of the user data to match the channel rate of the narrowband network may also be provided.

Abstract: A method and system are provided for real-time special effects processing, compressing and storing video signals. A memory is provided for storing plural frames including a sequence of one or more uncompressed frames. One or more processors are also provided for forming a sequence of special effect frames. Each special effect frame is a combination of one uncompressed frame (stored in the memory) and frame data other than the uncompressed frame (which combination can be a linear combination). The processor(s) also compresses the special effect frame.

Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of dividing the integrated circuit design with lines in a first direction and lines in a second direction, forming a routing graph having vertices and edges, wherein vertices correspond to locations where lines in the first direction cross lines in the second direction, routing nets as a function of said routing graph with parallel processors operating substantially simultaneously, determining the relative wire congestion among different areas in the integrated circuit design, and rerouting nets passing though areas with a relatively high wire congestion.

Abstract: An optical waveguide extends vertically within the interior of an IC-like structure to route optical signals between horizontal waveguides in different layers of horizontal optical interconnects. A light reflecting structure is positioned at the intersection of the horizontal and vertical waveguides to reflect the light. Multiple horizontal waveguides may join the vertical waveguide at a common intersection, to form a beam splitter or a beam combiner. Optical signals from one horizontal waveguide are diverted within the IC-like structure into another horizontal or vertical waveguide. The waveguide is formed with a light reflective structure at an intersection of the horizontal and vertical waveguides, and the waveguide is completed using damascene fabrication techniques.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.