Patents Assigned to LSI Logic
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Patent number: 6300800Abstract: An integrated circuit output buffer includes a core terminal, a pad terminal, a pad pull-up transistor, a pad pull-down transistor, a pull-up voltage protection transistor, and a selectively conductive pad voltage feedback path. The pad pull-up transistor and the pad pull-down transistor are coupled to the pad terminal and are biased to respectively charge and discharge the pad terminal in response to a data signal received on the core terminal. The pull-up voltage protection transistor is coupled in series between the pad pull-up transistor and the pad terminal and has a control terminal and a well terminal. The selectively conductive pad voltage feedback path is coupled between the pad terminal and the well terminal of the pull-up voltage protection transistor.Type: GrantFiled: November 24, 1999Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventors: Jonathan A. Schmitt, Eric W. Eklund
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Patent number: 6300769Abstract: Accordingly, there is disclosed herein a fast word compare circuit suitable for use in a BIST or BISR environment. In one embodiment, the comparator includes a front end and a zero-detector circuit. The front end receives two or more words and compares them bitwise, generating a set of bit match signals that indicate which bits match. The zero detector receives the bit match signals from the front end and asserts an output signal when all the bit match signals indicate a match. The front end may consist of a set of exclusive-or (XOR) gates, each configured to generate a bit match signal from respective bits of the input words. The zero detector may include a set of bit transistors coupled in parallel between a first node and ground. Each bit transistor receives a respective bit match signal and conducts when the respective bit match signal is asserted.Type: GrantFiled: December 17, 1999Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventor: Tuan Phan
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Patent number: 6301598Abstract: A square estimator computes an estimate of the square of an input number. The input number preferably is provided to combinational logic that logically manipulates the bits of the input number to generate an estimate of the square of the input number. The level of accuracy of the square generator can be programmed or predetermined by including or enabling various term generator logic units. Each term generator logic unit produces an output value that, when added to all of the other output values from the other term generators, provides an estimate of the square of the input number. Additionally, negative correction logic can also be incorporated into the square estimator for producing a negative correction value that when added to the estimate values from the various term generators, permits the square estimator to estimate the square of negative numbers as well as positive numbers.Type: GrantFiled: December 9, 1998Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventors: Gregg Dierke, Darren D. Neuman
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Patent number: 6301264Abstract: A data conversion circuit and method are disclosed for converting an N-bit data stream to an M-bit data stream. A FIFO memory device having multiple N-bit memory locations receives as an input consecutive N-bit sets of data and stores each consecutively received N-bit set of data in consecutive memory locations. A write pointer identifies a next available memory location at which the next N-bit set of data is to be stored. A first read pointer identifies a first memory location containing a first portion of a first M-bit set of data. A second read pointer identifies a second memory location containing a last portion of the first M-bit set of data. Provided as the first M-bit set of data are each of the N-bit memory locations between and including the memory location identified by the first read pointer and the memory location identified by the second read pointer.Type: GrantFiled: June 2, 1998Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventor: Jeffrey J. Holm
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Patent number: 6301304Abstract: An inverse quantizer is provided with a reduced bit-width. In one embodiment, the inverse quantizer receives quantized DCT coefficients in sign+magnitude form with 1+11 bits of resolution, and produces reconstructed DCT coefficients with 1+11 bits of resolution. Although this is less than the theoretical minimum bit-width required to represent the entire reconstructed DCT coefficient range [−2048, 2047] mandated by the MPEG standard, certain IDCT implementations will maintain IEEE compliance when the −2048 value is replaced with −2047. (An example of one such implementation is provided in a co-pending application.) This reduces the range to [−2047, 2047]. In one embodiment, the inverse quantizer includes a dead-zone expander, a quantization multiplier, a mismatch controller, and a bit-width reducer. The dead-zone expander receives quantized coefficients with 1+11 bits of resolution, doubles them, and then increases their magnitude by one.Type: GrantFiled: June 17, 1998Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventors: Tai Jing, Surya Varanasi
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Patent number: 6301176Abstract: The circuit generally comprises a bit line, a complementary bit line, a memory cell and a read circuit. The memory cell may be configured to (i) discharge the bit line in response to a memory sense period and (ii) charge the complementary bit line in response to said memory sense period. The read circuit may be configured to (i) precharge the bit line prior to the memory sense period, (ii) discharge the complementary bit line prior to the memory sense period, and (iii) detect when the bit line and the complementary bit line achieve a predetermined voltage separation in response to the memory sense period. The circuit may be used in asynchronous memories.Type: GrantFiled: December 27, 2000Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventor: Jeffrey S. Brown
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Patent number: 6300663Abstract: A static random-access memory integrated circuit formed on a single substrate includes a storage IGFET formed on the substrate and having a first area and a first capacitance. A gating FET formed on the substrate has an area substantially equal to the first area with a capacitance substantially less than the first capacitance. In one aspect, the storage FET has a substantially thicker gate oxide than the gating FET. In another aspect, the gate oxide of one of the FETs is formed from a different material than that of the other FET. A method for fabricating such IGFETs on a single substrate is also provided in which source and drain regions are formed adjacent the surface of the substrate. A first layer of gate oxide is formed on the surface of the substrate over the channels of the first and the second FETs. The first layer of gate oxide is then covered by a nitride layer which is thereafter etched away over the channel of one of the FETs.Type: GrantFiled: June 15, 2000Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventor: Ashok K. Kapoor
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Patent number: 6299723Abstract: An anti-airlock apparatus for filters comprises a process bath for processing wafers, a filtration unit incorporating a filter for preliminarily filtering a process solution before said processing and connected to a first deaeration line, and a tank body provided on the primary side or the filtration unit and connected to a second deaeration line, wherein at least said filtration unit and tank body are connected to each other via a pipeline, and a valve of the first deaeration line and a valve of the second deaeration line are separately operated and said first and second deaeration lines are directly connected to the most upstream side of the process solution.Type: GrantFiled: May 28, 1999Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventors: Hideaki Seto, Haruhiko Yamamoto, Nobuyoshi Sato, Kyoko Saito
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Patent number: 6301428Abstract: In accordance with a first embodiment of the invention, a method for editing video is provided. In accordance with the invention, a previously compressed first digital video bit stream is decoded to obtain a decoded digital video signal. In response to statistical values which characterize the previously compressed first digital video bit stream, the decoded digital video signal is re-encoded to form a second digital video bit stream such than an ending fullness of a vbv does not fall below a predetermined threshold. Optionally, an effect may be added to the decoded digital video signal before re-encoding. A second embodiment of the invention is directed to a method for splicing a first compressed digital video bit stream and a second compressed digital video bit stream. The first compressed digital video bit stream has a plurality of entry points.Type: GrantFiled: December 9, 1997Date of Patent: October 9, 2001Assignee: LSI Logic CorporationInventor: Elliot N. Linzer
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Patent number: 6297550Abstract: A semiconductor package (100) includes a bondable aluminum heatspreader (130) made from anodized aluminum, thereby forming an anodization layer (132) on the surface of the heatspreader. Portions of the anodization layer are removed, e.g., by grinding, in order to provide an attachment area (124) to which a wire (122) or beam may be bonded in order to electrically connect the heatspreader to a desired voltage potential, such as a ground potential or a positive or negative potential. The heatspreader is thermally bonded to a semiconductor die (102) housed within the package. The anodized aluminum heatspreader thus not only removes and dissipates heat from the semiconductor die, but also functions as a voltage or ground plane within the semiconductor package.Type: GrantFiled: April 1, 1998Date of Patent: October 2, 2001Assignee: LSI Logic CorporationInventors: Chok J. Chia, Patrick Variot, Maniam Alagaratnam
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Patent number: 6297558Abstract: The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent to a pad on which the slurry is disposed. The pad may be rotated to force the slurry into the recess. After the slurry is densely packed into the recess, the slurry may be cleaned from the topological surface exclusive of the recess. The slurry may be heated in order to remove the liquid portion of the slurry. The resulting topological surface is planar since a recess no longer exists therein. The technique hereof may be especially usefull for filling a recess that forms in the surface of a plug or in the surface of a fill dielectric disposed within a trench. Such recesses may form as a result of CMP or etchback.Type: GrantFiled: December 2, 1999Date of Patent: October 2, 2001Assignee: LSI Logic CorporationInventor: Michael J. Berman
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Patent number: 6297555Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.Type: GrantFiled: December 22, 1998Date of Patent: October 2, 2001Assignee: LSI Logic CorporationInventors: Joe W. Zhao, Wei-Jen Hsia, Wilbur G. Catabay
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Patent number: 6294840Abstract: Provided is a two-step, dual-thickness solder mask material on the substrate surface. The material is preferably applied in a series of screenings: A first screening of the solder mask material in the region where the chip will be placed, and a second screening of solder mask surrounding the place on the substrate surface where the die will be placed, normally over the outside edge regions of the substrate surface. The thickness of this first screening of solder mask may be from about 10 to 20 microns, while the thickness of the second screening of solder mask is about conventional thickness for a solder mask, for example from about 30 to 40 microns.Type: GrantFiled: November 18, 1999Date of Patent: September 25, 2001Assignee: LSI Logic CorporationInventor: John P. McCormick
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Patent number: 6294937Abstract: 3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.Type: GrantFiled: May 25, 1999Date of Patent: September 25, 2001Assignee: LSI Logic CorporationInventors: Harold S. Crafts, David P. Steele
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Patent number: 6295636Abstract: A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL level description into gate-level description comprising the steps of identifying hardware elements in the RTL code, determining key pins for each of said identified hardware elements, extracting design structure and hierarchy from the RTL code, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design and generating script to cause a logic synthesis tool to repeat said bottom-up and said top-down applications until certain predetermined constraints are satisfied.Type: GrantFiled: February 20, 1998Date of Patent: September 25, 2001Assignee: LSI Logic CorporationInventor: Guy Dupenloup
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Patent number: 6292283Abstract: An audio/video device including an infrared transceiver for transmitting and receiving configuration data is described, along with an associated configuration method. The audio/video device includes audio/video circuitry, a control unit, and an infrared transceiver. The audio/video circuitry receives input presentation data (i.e., video and/or audio data) and performs an audio/video operation (e.g., decoding, filtering, amplification, etc.) upon the input presentation data in order to produce output presentation data. The control unit is coupled to and controls the operations of the audio/video circuitry and the infrared transceiver. The infrared transceiver transmits and receives configuration data via infrared signals, wherein received configuration data is used to configure operation of the audio/video circuitry. The infrared transceiver includes an infrared transmitter and an infrared receiver.Type: GrantFiled: July 17, 1998Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventor: Brett J. Grandbois
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Patent number: 6292931Abstract: A method of determining circuit characteristics of an integrated circuit design defined by RTL code, said method comprising the steps of identifying hardware elements in the RTL code, determining key pins for said identified hardware elements, and extracting critical design structure from the RTL code. The hardware elements identified include flipflops, latches, tristate buffers, bidirectional buffers and memories. The critical design structures include design hierarchy and nets, including clock nets, multiply-driven nets, reset nets, and RAM write enable nets.Type: GrantFiled: February 20, 1998Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventor: Guy Dupenloup
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Patent number: 6292924Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph.Type: GrantFiled: November 5, 1997Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventors: Ivan Pavisic, Anatoli A. Bolotov, Alexander E. Andreev, Ranko Scepanovic
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Patent number: 6292929Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.Type: GrantFiled: November 22, 1999Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventors: Ranko Scepanovic, Ivan Pavisic, James S. Koford, Alexander E. Andreev, Edwin Jones
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Patent number: 6292409Abstract: A programmable input/output (I/O) pad internal resistive pull circuit assembly capable of providing programmable chip (SCSI Controller) initialization is disclosed. In an exemplary embodiment, the assembly includes a non-volatile memory cell disposed in said non-volatile memory device. First and second transistor devices are coupled to the non-volatile memory cell. The non-volatile memory cell is capable of being programmed for providing at least one of a pull-up and a pull-down on an associated signal line of the non-volatile memory device thereby furnishing a predetermined reset value to a controller device of the control system.Type: GrantFiled: December 12, 2000Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventor: Paul J. Smith