Abstract: A method for routing a net on an integrated circuit device, said method comprising the steps of creating a list of basis elements of the net, said basis elements being defined by a predetermined size limitation, determining a complexity value for each basis element as a function of the distance between pins in the basis element, forming a hypertree for the net as a function of complexity values of basis elements so determined, and routing the net as a function of the hypertree.

Abstract: A vertical plate capacitor is formed in interlayer dielectric material which separates conductors of upper and lower interconnect layers by a method which avoids the accumulation of residual materials from chemical mechanical polishing (CMP). The method comprises the steps of forming a capacitor via into the interlayer dielectric material, forming a first conductive layer having a U-shaped portion into the capacitor via, forming U-shaped capacitor dielectric material in the U-shaped portion of the first conductive layer, forming a second conductive layer having a U-shaped portion in the U-shaped capacitor dielectric material, filling an interior of the U-shaped portion of the second conductive layer with a plug material, and polishing after the capacitor via is entirely occupied by these elements.

Abstract: The purpose of the present invention is to improve the rapid SPU playback scheme in a DVD player. In order to achieve this end, the method in accordance with the invention comprises the steps of: comparing the system time clock (STC) with the execution time of an instruction set that provides display control in the sub-picture units (SP_DCSQ_STM_N), forcing the display of pixel data (PXD) contained in a sub-picture unit to suspend operation and to proceed to instruction interpretation of the instruction set in a next sub-picture unit if said comparison means determines, when the sub-picture units are being rapidly played back, that the system time clock performing a rapid increment operation has a greater value than the execution time of the instruction set at least one ahead (SP_DCSQ_STM_N+1) and continuously repeating the instruction interpretation until the execution time of the instruction set coincides with the system time clock.

Abstract: A method of removing particles adhering to a surface of a semiconductor wafer including the steps of: providing a container having a drain valve; positioning the semiconductor wafer in the container; directing a jet stream consisting of water against the surface of the semiconductor wafer; removing particles adhering to the surface of the semiconductor wafer by scrubbing the surface of the semiconductor wafer with a brush while the jet stream of water is directed against the surface of the semiconductor wafer; closing the drain valve while the jet stream of water is directed against the semiconductor wafer, wherein the water accumulates in the container to thereby completely immerse the brush and the semiconductor wafer in the water in the container; and maintaining the brush and the semiconductor wafer completely immersed in the water from the jet stream for a predetermined period of time.

Abstract: A digital filter in an oversampling converter is tuned to compensate for the non-ideal frequency response of a transducer coupled to the converter. In the A/D path, the filter coefficients of the decimation filter in a sigma-delta converter are tuned to compensate for the transducer. In the D/A path, the filter coefficients of the interpolation filter of a sigma-delta converter are tuned to compensate for the transducer. Filter coefficients may be statically defined in circuitry or programmable from values stored in a storage memory. Compensation may also be accomplished by tuning capacitor ratios in a switched capacitor filter, which is typically integral to the D/A path of an oversampling converter.

Abstract: Synchronization (sync) marks on a digital-versatile disk (DVD) optical disk are initially detected and later used to adjust bit timing after jitter has occurred. Each DVD physical sector contains many sync marks in a predefined sequence. Each sync mark has a sync-code field that varies for the sync marks in a sector, and a fixed sync pattern that is constant for all sync marks. The first sync mark is detected at initialization by detecting a previous sequence of sync codes of sync marks that precede the first sync mark. The sequence is programmable so that one to seven sync marks are in the sequence searched for. Detection for sync marks with bit errors can still occur since a programmable number of bit errors are allowed in each sync code and in the fixed sync pattern. One of the sync codes can be missed in the sequence and detection still made, allowing tolerance of errors in the sync marks when longer sequences of sync codes are matched.

Abstract: A polishing table 11 in the CMP apparatus 10 has a diameter smaller than the diameter of a polishing pad 12. The polishing pad 12 is disposed on the polishing table so as to cover the entire top surface of the polishing table 11. A space 13 is formed between outside of the outer peripheral surface of the polishing table 11 and under the outer peripheral bottom surface portion of the polishing pad 12 projecting outside from the edge of the polishing table 11. A trough 14 with an opening 14a on top thereof as a device for withdrawing the used slurry is disposed around the outer peripheral surface of the polishing table 11 so as to be located a part thereof in the space 13.

Abstract: Reusable tags are assigned to read and write requests on a tagged access synchronous bus. This allows multiple reads to be queued and overlapped on the tagged access synchronous bus to maximize data transfer rates. Writes are buffered to similarly allow multiple writes to be over-lapped. All data transfers on the tagged access synchronous bus typically would default to a cache block amount of data, with critical word first and early termination capabilities provided to permit processor execution to proceed without waiting for an entire cache block to be loaded. The tagged access synchronous bus architecture thus allows the system to take full advantage of high speed memory devices such as SDRAMs, RDRAMs, etc. while decoupling the bus data transfers from processor execution for increased overall system performance.

Abstract: A system and method described for avoiding catastrophic error sequences in a media code sequence of symbols for data storage on a storage medium according to EPRML. The system and method includes modulation encoding user data which is to be stored on the storage medium using a modulation encoder. The modulation encoder outputs a channel code modulation output symbol sequence. The modulation code is defined according to a modulation criteria wherein the set of all possible modulation output symbol sequences is constrained in a manner which excludes certain excluded modulation output symbol sequences. A precoder precodes the channel code modulation output symbol sequence according to a precoding transfer function.

Abstract: The present invention provides for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.

Abstract: A dual-phase clock divider circuit provides the ability to generate high speed complementary clocks with low skew. The dual-phase clock divider circuit runs off a single clock input, such as provided by a high speed VCO. This eliminates the effect of clock skew in the highest speed portion of the circuit. The dual-phase clock divider then generates complementary outputs of low skew to be used by other clocked elements.

Abstract: In a storage target device controller capable of managing multiple command contexts, methods and associated apparatus are provided for automatically managing the plurality of contexts using a state machine model. The state machine model is operable on a target device controller having an active context register set for processing of the presently active transfer on the host channel and an inactive context register set for storing an inactive context. The active context register set and inactive context register set are rapidly and automatically swapped by operation of the state machine model to resume or start processing of an inactive context. Additional inactive contexts are stored in a buffer memory associated with the target device controller. The inactive context register set is automatically stored into a selected one of the additional inactive contexts or loaded from a selected one of the additional inactive contexts by operation of the state machine model of the present invention.

Abstract: A MOSFET having a buried channel structure and an adjacent surface channel structure between a source region and a drain region. The surface channel structure is preferably formed adjacent the source region via angular implantation techniques. By combining the advantages of the surface channel device with the buried channel device, the resulting hybrid MOSFET structure has improved drive current and switching characteristics.

Abstract: A unified memory system includes a processor, a memory controller, a plurality of bus transactor circuits and a shared memory port. A processor bus is coupled between the processor and the memory controller. A first multiple-bit, bidirectional system bus is coupled between the shared memory port, the memory controller and the plurality of bus transactor circuits. A second multiple-bit, bidirectional system bus is coupled between the memory controller and the plurality of bus transactor circuits.

Abstract: A precise timing delay method and apparatus. A phase-locked loop (PLL) in combination with a timing reference is used to calibrate a precise delay. These delays are then duplicated throughout the chip and controlled by the same current as in the PLL. This makes the delays process, voltage, and temperature insensitive. The delays can be programmed by selecting the desired delay through a multiplexer. Providing high precision delays are particularly advantageous for use in devices such as computer bus isolators.

Abstract: Integrated circuit chip (IC) design and fabrication is a complex process requiring many stages including elaborate cell placement processes. The present invention provides a method and apparatus to facilitate the placement of cells on the surface of an integrated circuit device. Specifically, the invention involves placement of one type of cells (such as logic cells, I/O cells or scan cells) apart from other types of cells. The present invention facilitates the placement of such cells by first parsing the netlist to remove all cells other than the specific type of cells that are to be placed.

Abstract: A method of polishing a first layer of a semiconductor wafer down to a second layer of the semiconductor wafer is disclosed. One step of the method includes polishing the first layer of the semiconductor wafer with a polishing surface having a chemical slurry positioned thereon. The polishing step causes an infrared spectrum to be emitted through the semiconductor wafer. Another step of the method includes detecting a rate of change of intensity level of the infrared spectrum and generating a control signal in response thereto. The method also includes halting the polishing step in response to generation of the control signal. Polishing systems are also disclosed which determine a polishing endpoint for a semiconductor wafer based upon an infrared spectrum generated due to a chemical slurry reacting with the semiconductor wafer.

Abstract: An on-chip voltage reference supply operates in the current domain rather than the voltage domain, implemented with a single diode drop to reduce power supply headroom requirements. A plurality of current generators generate currents representing a first design voltage. A gain circuit responds to the currents to supply a gain voltage representing the sum of the first design voltages. A summing circuit sums the gain voltage and a second design voltage to derive the predetermined reference voltage.

Abstract: Semiconductor die pad design consisting of an I/O cell where the outside bond site is connected to the cell's active signal, the second inside bond site is discrete and connected to one of the I/O power supplies Vdd or Vss, and the third inside bond site is discrete and connected to the compliment of the second pad site. The I/O cell design is universal to traditional wire-bonding assemblies and flip-chip assemblies.

Abstract: Apparatus and methods which allow multiple storage controllers sharing access to common data storage devices in a data storage subsystem to access a centralized intelligent cache. The intelligent central cache provides substantial processing for storage management functions. In particular, the central cache of the present invention performs RAID management functions on behalf of the plurality of storage controllers including, for example, redundancy information (parity) generation and checking as well as AID geometry (striping) management. The plurality of storage controllers (also referred to herein as RAID controllers) transmit cache requests to the central cache controllers. The central cache controllers performs all operations related to storing supplied data in cache memory as well as posting such cached data to the storage array as required.