Abstract: Methods and associated apparatus for performing concurrent I/O operations on a common shared subset of disk drives (LUNs) by a plurality of RAID controllers. The methods of the present invention are operable in all of a plurality of RAID controllers to coordinate concurrent access to a shared set of disk drives. In addition to providing redundancy features, the plurality of RAID controllers operable in accordance with the methods of the present invention enhance the performance of a RAID subsystem by better utilizing available processing power among the plurality of RAID controllers. Under the methods of the present invention, each of a plurality of RAID controllers may actively process different I/O requests on a common shared subset of disk drives. One of the plurality of controllers is designated as primary with respect to a particular shared subset of disk drives.

Abstract: An improved data processing system and in particular an improved data processing system that more effectively manages a shared resource within a data processing system. More specifically, a method and apparatus for managing access to a shared resource between a plurality of devices simultaneously requesting access to the shared resource. The present invention implements a design that combines a priority configuration and a shifting sequential configuration. The access is controlled by an arbiter that determines access to the shared resource by granting first, to priority devices and then to the highest priority shifting sequential device requesting access within one clock cycle of a device terminating its request for access to the shared resource.

Abstract: A circuit in a memory device for precharging at least one bit line before a data read operation of the memory device is complete. The circuit includes a sense amplifier having at least one input and at least one output. The bit line is connected to the input of the sense amplifier via column decode logic, and a precharge circuit is connected to the bit line. An input keeper is connected to the sense amplifier inputs and is in communication with the precharge circuit and column decode logic. The input keeper holds a content of the bit line at the sense amplifier inputs and causes the precharge circuit to precharge the bit line as the content of the bit line propagates to the output of the sense amplifier.

Abstract: The present invention includes at least two variable-resistive devices, such as transistors, coupled to a resistive device, such as a resistor. The transistors are configured so that feedback voltage generated by respective currents of the transistors is applied to the gate of at least one of the transistors. The electrical characteristics of the other transistor changes proportionately greater than the characteristics of the one transistor. With this configuration, a variation-compensated current device is provided.

Abstract: In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream cipher has an input to receive scrambled video data, and an output coupled to a block cipher for providing descrambled data, the stream cipher comprises shift register means for holding input data coupled to a first mapping logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means comprising shift register means for holding the output of the stream cipher means and a second logic mapping mechanism, comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence being arranged to carry out similar logical steps.

Abstract: A video decoder which uses a dynamic memory allocation scheme having end-of-frame (EOF) tokens for decoder-display synchronization. The EOF tokens advantageously allow for decoding and display of variable-sized images with a fixed dynamic memory allocation architecture. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a fixed-size monitor. To conserve memory, the bitstream decoder only stores anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments. Free memory segments are determined by examination of a free segment register, and pointers to the memory segments having image data are passed to the display processor via the FIFO buffers.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that wire routine be done correctly to avoid any congestion of wires. Placement of the cells and the routing of the wires to avoid congestion can be accomplished by determining congestion of various regions of the IC's after an initial placement of the cells and routing of the wires. The present invention discloses a method and apparatus to determine the congestion of the regions and a technique to increase the fictive heights (or, the "working height", or the "working size") of the cells for repeating the placement of the cells if the current placement and routing leads to congestion. The present invention provides for a method of defining regions and line segment.

Abstract: A processor is provided with an interrupt capture and hold mechanism. In one embodiment, a processor includes an instruction pipeline having stages for executing instructions. In the event of an exception, the instructions in the pipeline are flushed or aborted. This requires that each stage in the pipeline receive and respond to an exception-causing signal. An interrupt is an exception causing signal which may be provided by circuitry external to the processor. To ensure that such a signal is asserted long enough for each stage in the pipeline to receive and respond to it, all external hardware interrupts are routed through an interrupt capture and hold mechanism, thereby advantageously preventing the causation of an undefined processor state with little added complexity.

Abstract: An electronic semiconductor device package, the package having: a substrate having a top and bottom surface and having traces; a die attached to the top surface of the substrate; first level interconnects of the die to the traces of the substrate; encapsulant which covers the die and first level interconnects; and a lid attached to the encapsulant, wherein the lid comprises at least one lid support which extends from the lid to the substrate.

Abstract: A scannable dynamic logic element includes a clock input, a test enable input, a data output, a precharge circuit, a boolean pull-down circuit and a test scan pull-down circuit. The precharge circuit is coupled between a first supply terminal and the data output and has a precharge control input coupled to the clock input. The boolean pull-down circuit is coupled between the data output and the second supply terminal and has a logic data input, a first evaluation control input which is coupled to the clock input and a first enable input which is coupled to the test enable input. The test scan pull-down circuit is coupled between the data output and the second supply terminal and has a test data input, a second evaluation control input which is coupled to the clock input and a second enable input which is coupled to the test enable input.

Abstract: An apparatus and method are presented for separating a stiffener member from a substrate of a flip chip integrated circuit package such that the substrate is not damaged. The apparatus includes a base plate for receiving an upper portion of the device package including the stiffener, and a hand tool for receiving a lower portion of the device package including the substrate. During use, the base plate engages the upper portion of the device package and the hand tool engages the lower portion. The hand tool is moved in relation to the base plate such that an adhesive layer joining the stiffener and substrate is broken (i.e., sheared), and the stiffener is separated from the substrate. As the adhesive layer is typically an amorphous polymer material which softens with increased temperature, the base plate is preferably heated prior to effecting the movement of the hand tool in relation to the base plate.

Abstract: A technique for reducing silicon defect induced transistor failures, such as latch-up, in a CMOS or other integrated circuit structure includes fabricating the integrated circuit structure on a substrate and implanting a buried layer beneath a surface of the integrated circuit. The buried layer implant is the final implanting step during fabrication of the integrated circuit structure. In another technique, fabricating the integrated circuit structure includes performing multiple sequential processes some of which are performed at elevated temperatures above about 500.degree. C. A buried layer is implanted beneath a surface of the integrated circuit. After implanting the buried layer, the substrate is subjected to a fabrication process at an elevated temperature above about 800.degree. C. only once. Propagation of defects, such as in-the-range defects or ion enhanced stacking faults, from the buried layer to other device layers during the fabrication process is reduced.

Abstract: A method and apparatus is disclosed for terminating a SCSI bus having a SCSI port, with the SCSI port having a first set of I/O terminals associated only with wide SCSI buses and a second set of I/O terminals associated with both wide SCSI buses and narrow SCSI buses. The method includes the steps of determining if a first reference signal is present on one terminal of the first set of I/O terminals; determining if a second reference signal is present on one terminal of the second set of I/O terminals; and terminating each terminal of the first set of I/O terminals while not terminating any terminals of the second set of I/O terminals (1) if the first reference signal is not detected in the first reference signal determining step, and (2) if the second reference signal is detected in the second reference signal determining step.

Abstract: A process of inhibiting a corrosion of metal plugs formed in integrated circuits is described. The corrosion inhibiting process includes providing a partially fabricated integrated circuit surface including the metal plugs on a polishing pad to carry out chemical-mechanical polishing, introducing slurry including a corrosion inhibiting compound on the polishing pad in sufficient concentration to inhibit corrosion of the metal plugs of the partially fabricated integrated circuit surface, and polishing the partially fabricated integrated circuit surface.

Abstract: The present invention advantageously provides a method for filling a recess with a slurry that exhibits electrical properties similar to those of the structure which has the recess. The topological surface that includes the recess may be placed adjacent to a pad on which the slurry is disposed. The pad may be rotated to force the slurry into the recess. After the slurry is densely packed into the recess, the slurry may be cleaned from the topological surface exclusive of the recess. The slurry may be heated in order to remove the liquid portion of the slurry. The resulting topological surface is planar since a recess no longer exists therein. The technique hereof may be especially useful for filling a recess that forms in the surface of a plug or in the surface of a fill dielectric disposed within a trench. Such recesses may form as a result of CMP or etchback.

Abstract: A computer-based method and system is disclosed that automates the design and layout of digital multiplier circuits. The preferred method utilizes an automatic design generator having a user interface which receives design requirements for a digital multiplier circuit design. A digital multiplier design generator receives the design requirements for the digital multiplier and retrieves relevant component implementations from a component library. Stored digital multiplier benchmarks are then retrieved from a benchmark memory and applied to corresponding digital multipliers to determine which of the various implementations optimally satisfies the user design requirements. Once the optimal digital multiplier implementation is selected, the digital multiplier design generator produces a logic design including a netlist and a physical design including design directives which are then used to place and route the digital multiplier as a finished layout.

Abstract: Disclosed are planar DRAM cells including a storage capacitor having a high dielectric constant capacitor dielectric. The DRAM cell also includes an access transistor having a gate dielectric which does not include the high dielectric constant material. A single polysilicon layer is employed to form the gate electrode of the access transistor and a reference plate of the storage capacitor. A disclosed fabrication process forms the high dielectric constant material that is limited to a capacitor region of the DRAM cell and then forms the gate dielectric over an entire active region including both the high dielectric constant material layer at the capacitor region and the semiconductor substrate at the access transistor region. In this manner, a high quality gate dielectric (e.g., silicon oxide) is formed at the access transistor region and a high dielectric constant dielectric layer (e.g., silicon nitride) is formed at the capacitor region.

Abstract: A system comprises translation software to convert non-tester-compatible simulation results into tester-compatible test patterns in a ATE system. An intermediate output of the system includes tester-compatible input stimulus for use in re-simulating a circuit design. The resulting simulation output data is tester-compatible, by definition, and can be used to generate tester-compatible test patterns that correspond to a verified simulation of the circuit design. Partnered time sets and signal state data are used in translation between tester-compatible and non-tester-compatible timings.

Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

Abstract: A process for compensating for degradation of a first polishing pad during polishing on the first polishing pad of a plurality of substrate surfaces that have substantially similar film stacks is described. The process includes: (a) characterizing a test polishing pad, which characterization includes determining changes in film removal rates of layers of the film stack during polishing of the plurality of the substrate surfaces on the test polishing pad; (b) polishing a first substrate surface on the first polishing pad, which is substantially similar to the test polishing pad, under a first set of polishing conditions; and (c) polishing a second substrate surface on the first polishing pad under a second set of polishing conditions. A difference between the second set of polishing conditions and the first set of polishing conditions is designed to minimize the changes in the film removal rates of the layers of the film stack and thereby compensate for degradation of the first polishing pad.