Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithography and an anti-reflective coating. The self-alignment allows the size and location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.

Abstract: An improved transceiver pair that are tightly integrated into a computer system. The transceiver pair include a base transceiver and a remote transceiver, with a high speed serial connection between them. The base transceiver has a base transmitter with a parallel input port for accepting parallel, encoded data and a serial output port for transmitting a serial, encoded data stream. The remote transceiver has a receiver with a serial input port for receiving the serial, encoded data stream and an audio/video output port for passing deserialized data to an audio and video control unit after decoding. The high speed serial connection links the base serial output port to the remote serial input port. The remote receiver further includes a feedback input port adapted for receiving feedback data forwarded from a sensor. The sensor may respond to palpable, optical or sonic input or to physical contact.

Abstract: Described is an improvement in a process wherein integrated circuit structures are formed on a front surface of a silicon substrate and at least one layer of copper is deposited on the front surface of the substrate to form a layer of copper interconnects, and wherein at least some copper is also deposited on the back surface of the substrate during this deposition. The improvement comprises: prior to the end of the formation of the integrated circuit structures, abrasively removing, from the backside of the substrate, copper deposited thereon during the deposition of copper on the front surface.

Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e.

Abstract: An audio decoder is described that can concurrently produce two synchronized outputs of a digital audio stream at different sampling rates and can provide for seamless switching between the rates. In one embodiment, the audio decoder includes a first output buffer, an arithmetic logic unit (ALU), a second output buffer, and a control module. The first audio buffer is configured to buffer a sequence of digital audio samples and to provide the first sequence of digital audio samples to an output device at 96 kHz. The arithmetic logic unit (ALU) is coupled to the first output buffer to retrieve the first sequence of digital audio samples and to convert the first sequence of digital audio samples into a decimated sequence of digital audio samples. The second output buffer is coupled to the ALU to buffer the decimated sequence of digital audio and to provide the decimated sequence of digital audio samples to a second output device at 48 kHz.

Abstract: A test structure according to the present invention provides a technique for determining defects as a function of metal layers. The technique is implemented by dividing the test structure into individual test blocks that correspond to certain metal layers. In the disclosed embodiment, for example, a test structure formed by a semiconductor process utilizing three layers of interconnect metal includes three distinct test blocks having similar or identical underlying test logic. In a first test block, the underlying test logic is predominantly connected by the first metal layer. In a second test block, the underlying test logic is predominantly connected by the second metal layer. In a third test block, the underlying test logic is primarily connected by the third metal layer. During the testing stage, test patterns are applied to each test block and the results are tabulated.

Abstract: Provided is a method and composition for reducing the rate of, and rendering more uniform the oxidation of alignment mark trench side walls by CMP slurry accumulating in an alignment mark trench during CMP processing. In a preferred embodiment, a nucleation layer of tungsten having an equiaxed grain structure with fine grain size and conformity is deposited over a conventionally applied bulk tungsten layer prior to commencing CMP operations. The fine grain size and equiaxed grain structure of this nucleation layer make it more resistant and more uniform in response to slurry attack. As a result, the tungsten trench profile remains a consistent and reliable alignment mark.

Abstract: A high order surface patch rendering system. A patch is rendered by subdividing a patch until the subpatches are sufficiently flat that they can be approximated by a quadrilateral, which can then be split diagonally and written to a rasterizer in the form of two triangles. In one embodiment, the patch rendering system receives rational coordinates (X,Y,Z,W) and attribute coordinates (color, opacity, texture) of control points of the Bezier surface patch. The patch rendering system divides and subdivides the surface patch by operating on the surface patch control points to produce subpatch control points. The rational coordinates of the control points are converted to spatial coordinates, and if the current subpatch is determined to be flat, the spatial coordinates and attributes of the subpatch corner points are provided to an output buffer in the form of triangle vertices with associated attributes.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. To reduce vertical congestion, the cells are moved from congested regions to uncongested regions. The present invention discloses techniques of defining regions as pieces and columns, determining the level of congestion in the regions, and the methods of moving the cells to different columns to reduce congestion while minimizing affects to wire routing. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns.

Abstract: A linear capacitor formed in an IC which has horizontally oriented interconnect layers that are vertically separated by dielectric material. Two separated metal plates of the capacitor are electrically connected to the conductors of different vertically-separated metal interconnect layers. The metal plates extend substantially vertically through the thicker dielectric material separating the interconnect layers, to provide a relatively high capacitance per unit of surface consumed. The interconnect layers to which the plates are connected are separated from a substrate of the IC by at least one layer of dielectric, to reduce parasitic effects. Forming the capacitor plates and the interconnect layers from at least some of the same metals simplifies construction and reduces cost, while providing linear response characteristics. Placing the capacitor between the interconnect layers avoids consuming space on the substrate to construct the capacitor.

Abstract: A method for managing power consumption of a digitizing panel includes the steps of: (a) applying a biasing voltage to the digitizing panel for a first period of time and ceasing to apply the biasing voltage to the digitizing panel for a second period of time; (b) determining whether a user has touched the digitizing panel during the first period of time; and (c) if the user has touched the digitizing panel during the first period of time, then applying a biasing voltage to the digitizing panel for a third period of time that is longer in duration than the first period of time and ceasing to apply the biasing voltage to the digitizing panel for a fourth period of time. An apparatus for implementing the method is also disclosed.

Abstract: A method for laying out input/output (I/O) pairs, each including an I/O cell and a pad, on an integrated circuit die. Size information is obtained for each of a first I/O pair and a second I/O pair. A minimum pad spacing criterion is obtained which specifies a minimum distance between the pad in the first I/O pair and an element of the second I/O pair, and the first I/O pair and the second I/O pair are laid out so as to satisfy the minimum pad spacing criterion. Also provided is a method for laying out pads for input/output (I/O) cells on an integrated circuit die in which size information is obtained for each of a first I/O cell pad and a second I/O cell pad. A minimum pad spacing criterion is obtained, and the first I/O cell pad and the second I/O cell pad are laid out so as to satisfy the minimum pad spacing criterion.

Abstract: A molded tape ball grid array package has a base structure including a heat conductive substrate and flex tape extending from opposing regions on a surface of the substrate with molded plastic material between the flex tape and the substrate. The flex tape has at least one conductive metal lead pattern which can be positioned on a side of the tape facing the substrate with a plurality of apertures exposing the conductive lead pattern from an opposing side of the tape for solder ball bonding. A semiconductor integrated circuit chip is mounted to a central portion of the substrate between the opposing regions of the flex tape with wire bonding interconnecting bond pads on the chip to the metal lead pattern. The chip and wire bonding are then encapsulated on the substrate. The structure is economical and permits high power dissipation from an integrated circuit. The molding process in fabricating the integrated circuit package is economical and readily implemented using injection molding.

Abstract: A phase-locked loop fabricated on an integrated circuit includes a phase/frequency detector, a charge pump, a filter node and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second frequency control inputs and a VCO output, wherein the first frequency control input is coupled to the filter node and the VCO output is coupled to the phase/frequency detector. The VCO has a first voltage-to-frequency gain from the first frequency control input to the VCO output and a second voltage-to-frequency gain from the second frequency control input to the VCO output. An off-chip filter input is coupled to the filter node for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first frequency control input and the second frequency control input and has a variable time constant. A time constant control circuit is coupled to the on-chip loop filter for controlling the variable time constant.

Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.

Abstract: A method and apparatus agitates an etchant contained within a bath. A wafer is immersed in a bath containing an etchant that is continuously mixed by release of a gas, preferably nitrogen, into the bath at a sufficient flow rate to agitate the etchant and assure a robust and substantially uniform selective etching process. The apparatus comprises valve assembly that receives gas from a source of gas under pressure and controls the flow rate and release pressure of the gas. In addition, the valve assembly contains an on/off valve that, when turned on, releases gas for a predetermined time period. Accordingly, a single operation of the on/off valve releases gas for the duration of a single selective etching cycle. A dispersion plate receives the gas from the valve assembly for release into the bath. The released gas passes through the baffle distribution plate that distributes the gas throughout the bath.

Abstract: A loop isolation circuit (LIC) to enable subdivision of a single daisy-chained communication loop (e.g., FC-AL) into smaller loops and to enable joining of smaller loops into a single larger loop. An LIC comprises essentially two multiplexors configured so as to permit controlled subdivision or joining of two loop portions. In a first selected state, the LIC subdivides a communication loop in which it is inserted into two loops. This configuration sacrifices accessibility among some devices previously on the larger loop for the benefit of enhanced bandwidth and reduced overhead due to node count. Bandwidth is enhanced by enabling simultaneous operation of two (or more) loop portions for establishing and communicating over logical circuit connections. However, when a failure of a redundant loop precludes access to devices, the LIC may be set to a second state to rejoin previously subdivided loops into a larger loop. This configuration restores access among all devices sharing common access to the larger loop.

Abstract: Disclosed is a non-volatile storage element that is defined between a bitline and a complementary bitline, and that can be accessed by a selected wordline is disclosed. The non-volatile storage element includes a high voltage latch that is configured to receive a pump voltage, and a reference voltage that is about half of the pump voltage. The non-volatile storage element also includes a storage cell that is configured to receive a logical programming value from the bitline and the complementary bit line when the wordline is driven high to turn on a first passgate and a second passgate. The storage cell further includes a capacitive transistor having its back gate, source and drain connected to a first terminal of the first passgate, and a tunneling transistor having its back gate, source and drain connected to a second terminal of the second passgate. The capacitive transistor and the tunneling transistor are configured to share a floating gate.

Abstract: The invention provides an exemplary computer component which comprises a battery pack and a container tray for receiving the battery pack. The battery pack in turn comprises a base and a cover which are slidable relative to each other to accommodate for the thickness of the battery pack when received within the container tray. Further, the container tray includes an aperture to provide access to the battery pack. A module is also provided and includes an interfacing device to allow the battery pack to be coupled to the module when the container tray is inserted into the module.

Abstract: A drive mechanism in a data storage apparatus for positioning and rotating a two-sided data storage medium. The drive mechanism includes at least one repeller adjacent each side of the data storage medium repelling at least one control element on the data storage medium thereby positioning the data storage medium. The drive mechanism also includes a plurality of driver elements located adjacent the data storage medium. Each of the driver elements is capable of selectably attracting or repelling the at least one control element on the data storage medium thereby causing the data storage medium to rotate while the data storage medium is positioned by the at least one repeller.