Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties. Also included in the disclosed system are methods and apparatus for capacity and utilization planning of the use of the floor, or the surface area, and the methods and apparatus for parallelizing the process of affinity based placements using multiple processors. Finally, method and apparatus for connecting the cells based on a Steiner Tree method is disclosed.

Abstract: An electrical interconnection structure on an integrated circuit is provided that has a) a substrate layer; b) a diffusion barrier on the substrate layer; c) a copper layer on the diffusion barrier; and d) a copper oxide layer on the copper layer. Methods of making such an interconnection structure is also provided. Such an interconnection structure may be used as a rectifier to prevent damage of sensitive devices from voltage spikes.

Abstract: An apparatus and method are presented for electrically determining whether delamination has occurred at one or more interfaces within a semiconductor wafer. The semiconductor wafer includes a test structure formed within dielectric layers upon an upper surface of a semiconductor substrate. The test structure includes an electrically conductive structure, a pair of electrically conductive contact plugs, and a probe pad. The conductive structure is formed within an opening in a first dielectric layer, and is in electrical contact with the upper surface of the semiconductor substrate. The conductive structure is preferably made up of the same vertical stack of layers of selected electrically conductive materials used to form interconnects within the semiconductor wafer. A second dielectric layer if formed over the first dielectric layer and the conductive structure. The pair of electrically conductive contact plugs extend vertically through respective holes in the second dielectric layer.

Abstract: An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self-test (BIST) circuitry and built-in-self-repair (BISR) circuitry. A BIST run is then performed on a predetermined portion of the integrated circuit to detect a set of faulty memory locations. The results of this first BIST run are stored. A second condition is applied to the die and a second BIST run is executed to generate a second set of faulty memory locations. The results of the second BIST run are stored and compared with the first result. If the results differ, the integrated circuit is rejected. Thus, a methodology for screening out field errors at the factory is disclosed using BIST/BISR circuitry.

Abstract: The invention relates to a method and apparatus for maintaining data/parity consistency in a RAID data storage system. The invention utilizes reserved disk storage space in the RAID array to log data necessary to restore data/parity consistency should an interruption event, such as a power failure, corrupt the data stored in a particular redundancy group. In one embodiment, the invention logs new data and new parity information to the reserved disk storage space before the new data and new parity information are written to the appropriate locations in the associated redundancy group. In this way, if an interruption event occurs when either the new data or the new parity information has already been written to the redundancy group but the other has not, the corresponding data and parity information stored in the reserved disk storage space can be used to restore data/parity consistency after the event has ended.

Abstract: A digital variable rate demodulator within a receiver operates close to the Nyquist rate. This serves to recover correct timing and filter adjacent channels. The samples of an incoming data signal are divided into phases and combined into phase vectors. Intermediate points within a given phase vector are determined by interpolation. The data is then converted into a weighted sum for the purpose of decimating down to the baud rate. The signal-to-noise ratio is then optimized by estimating the likelihood of occurrence of a given symbol within the waveform and filtering the near Nyquist data rate down to a one sample per symbol data rate.

Abstract: A device for removing a heatspreader from an integrated circuit package (ICP) according to the present invention. The device includes a base piece that is preferably made of a suitably rigid and thermally conductive base material such as tool steel. The base piece defines a base cavity that is adapted to receive and engage the heatspreader. The depth of the base cavity is approximately equal to a thickness of the heatspreader. The device further includes a top piece comprised of a suitable top material such as tool steel. The top piece includes a body portion from which an elongated member or handle extends. The body portion of the top piece defines a top cavity adapted to receive and engage the integrated circuit package. The elongated member is suitable for manipulating the body portion of the top piece to apply a torquing force to the ICP package when it is engaged in the top cavity.

Abstract: A RAID controller integrated into a single chip. The RAID controller chip includes a general purpose RISC processor, memory interface logic, a host CPU PCI bus, at least one back-end I/O interface channel, at least one direct memory access (DMA) channel, and a RAID parity assist (RPA) circuit. The RAID chip enables higher integration of RAID functions within a printed circuit board and in particular enables RAID function integration directly on a personal computer or workstation motherboard. The back-end I/O interface channel is preferably dual SCSI channels. The RAID chip is operable in either of two modes. In a first mode, the chip provides pass through from the host CPU interface directly to the dual SCSI channels. This first mode of operation, a SCSI pass-through mode, allows use of the chip for non-RAID storage applications and enables low level manipulation of the disk array in RAID applications of the chip.

Abstract: A method and apparatus for generating an interrupt signal. A counter value is decremented each time a task is completed by a slave processor. The counter value is incremented each time a task is read by the slave processor. A delay value is set using the counter value. An interrupt is generated after a period of time set by the delay value has passed. The counter value is compared to a threshold value. The interrupt is generated upon detecting a condition in which the counter value is less than the threshold value or when the completion queue is full instead of after the period of time.

Abstract: A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in charge stored on the capacitors. The adverse influences of noise are reduced or eliminated because the noise will generally equally effect both of the complementary capacitors, as well as complementary bit lines connected to the capacitors. Differential sensing of the bit line signals also avoids the influence of noise. A capacitor reference potential conductor distributes substantially equal capacitor reference voltage to each capacitor to allow each capacitor to charge and discharge more uniformly under the influence of noise.

Abstract: An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil.

Abstract: When a mobile communication unit (e.g. a cellular telephone) is powered up, the unit must lock on to a local base station, or "acquire" a base station signal, to enable the user to send and receive calls. To lock on a local base station, the mobile unit must determine the delay at which the base station is sending the pseudo random (PN) code. This process is called the "acquisition." The current art of acquiring a base station involves searching the possible code phases, or delays, one by one until the first signal is found. However, multiple base stations may be available to the mobile user, and the first found pilot signal may not be the strongest and may not be from the nearest base station. The present invention discloses a method and apparatus for searching all possible PN code phases and selecting the strongest phase instead of selecting the first phase.

Abstract: A method provides an on-chip repair technique to fix defective row or I/O memory lines in an ASIC memory array with redundancy row or I/O memory lines. The method employs progressive urgency and dynamic repair schemes to optimize the allotted time for repairing defective row and I/O memory lines. Progressive urgency scheme increases the need to repair relative to the available redundancy row or I/O memory lines over the entire repairing time. Dynamic repair executes a mandatory-row or a mandatory-I/O repair as defective row or I/O memory lines are detected. In addition, a recurrence error reroutes the address location of a redundancy memory line to another address location of another redundancy memory line in the event that such redundancy memory line itself is defective, and thus requires further repair.

Abstract: MOS functional devices and electrostatic discharge protection devices are formed on a substrate having a relatively low-resistance area beneath the functional devices to inhibit latch-up of the functional devices and a relatively high resistance area beneath each electrostatic protection device to reduce the snapback holding voltage of each electrostatic discharge protection device.

Abstract: A semiconductor device package is presented for housing an integrated circuit which includes bonding fingers located within a conductive ring structure and routed to device terminals on an underside surface of the semiconductor device package. The semiconductor device package includes a die area defined upon a planar upper surface, a conductive ring surrounding the die area, and a first set of bonding fingers arranged within the conductive ring. The die area is dimensioned to receive the integrated circuit. The conductive ring may be a power ring or a ground ring. The conductive ring and the first set of bonding fingers are located within a first signal layer adjacent to the upper surface. A set of bonding pads which serve as device terminals reside within a second signal layer adjacent to a planar underside surface.

Abstract: The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primary bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.

Abstract: Magnetic sensors are positioned adjacent a semiconductor integrated circuit under test while the circuit is subjected to selected electrical stimuli for purposes of failure analysis. The magnetic image data can be acquired from one or more selected locations about the circuit without any physical connection. By comparing the magnetic sensor information to a predetermined database of magnetic information acquired from known devices, failure modes can be identified. Conventional tester equipment can be used for providing the electrical stimuli to the device under test.

Abstract: A storage device is described for reading data from a hard disk drive wherein delays due to rotational latency are substantially reduced. The storage device includes a platter having a substantially planar annular surface with a geometrical center. On the platter are a plurality of generally arcuate concentric tracks. Each of the tracks is divided into a plurality of sectors that are radially outwardly disposed from the geometrical center of the platter and are bounded by radii extending from the geometrical center. Original data is written on at least one of the sectors. Further, a copy of the original data is maintained at a fixed azimuth angle from the original data during rotation of the platter about the center.

Abstract: A process for fabricating a trench filled with an insulating material in a surface of an integrated circuit substrate is described. One step of the process includes defining a masking layer on a composite layered stack above a region to be protected on the integrated circuit substrate surface. The composite layered stack includes a layer of a first material and a polishing stopping layer. The layer of the first material has a polishing rate by chemical mechanical polishing that is greater than a polishing rate by chemical mechanical polishing of the insulating material. Another step of the process includes etching through the composite layered stack and the integrated circuit substrate to form the trench in the integrated circuit substrate surface and depositing the insulating material on the integrated circuit substrate surface such that the trench is filled with the insulating material.

Abstract: A method and apparatus for maintaining automatic termination of a bus in the event of failure of a host computer are disclosed. The method includes the steps of (a) powering a first termination control circuit and a first terminating circuit of the first bus controller with the bus; (b) generating a first control signal (1) that is of an enable state if the first bus controller is located at an end of the bus, and (2) that is of a disable state if the first bus controller is located in a middle portion of the bus; (c) coupling the first terminating circuit to the bus if the first control signal is of the enable state; and (d) decoupling the first terminating circuit from the bus if the first control signal is of the disable state.