Abstract: A driver circuit has first and second output drivers, monitor circuitry for deriving control signals related to driven signal levels, and supply circuitry responsive to the control signals for controlling the supply voltage to the output drivers. The monitor circuitry can be connected to monitor the voltage at the supply inputs of the output drivers for deriving the control signals. Alternatively, the monitor circuitry can be connected directly to monitor driven output levels from the drivers. In the latter case, the output levels to be monitored are rectified. The monitor circuitry can comprise first and second operational amplifiers for comparing a monitored voltage from first and second output drivers, respectively, to a first and second reference voltages, respectively. The supply circuitry can comprise first and second constant current sources, for example field effect transistors.

Abstract: A wireless communication device may take the form of a cellular telephone, of a portable personal communication device, or even of a desk top personal computer which is equipped to communicate over the wireless cellular communication system in effect in a particular area. The wireless communication device is configured to self-adapt to various operating frequencies and communication protocols which may be present in the cellular communication environment so that the device is able to provide communications in several service areas even though the frequencies of operation and the communication protocols in use in the service areas may be incompatible with one another.

Abstract: Disclosed is a method and apparatus for facilitating the decomposition of organometallic compounds such as TEOS in chemical vapor deposition reactors in order to form deposition films. The method generally includes: (1) introducing an organometallic compound and ozone molecules to a chemical vapor deposition reactor; (2) directing ultraviolet radiation into the chemical vapor deposition reactor to increase the rate at which oxygen atoms are formed from the ozone molecules present in the chemical vapor deposition reactor; and (3) decomposing the organometallic compound to form a deposition layer. The organometallic compound decomposes at an accelerated rate due in part to an increased amount of hydroxyl radicals present in the chemical vapor deposition reactor.

Abstract: A system for proportionally partitioning multiple groups of cells on the surface of a semiconductor chip into subregions is disclosed herein. The cell groups are separated by dividing lines, and the system comprising a calculator which determines an offset of the cut line from the dividing line; a shifter which moves the location of said groups of cells by the offset such that the cut line coincides with the dividing line; and an overflow evaluator and compensator which shifts any cells outside said region to an edge of said region.

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: The present invention provides an analytical solution for voltage drop and current density calculation based on design-specific current consumption. The new technique calculates voltage drop and current density at all desired points of the power supply mesh. One application of the method is power mesh sizing by scaling the mesh resistance by the ratio between allowed voltage drop budget and the maximum of the calculated voltage drop. The designer can easily obtain the maximum allowed resistance of a uniform mesh which meets exactly the voltage drop budget, taking into account the design-specific spatial distribution of current consumption. Since the computational cost of the new methodology is negligible, e.g. as compared to prior art methods of analysis, this invention is suitable for implementation embedded in an RTL floorplan tool for fast, interactive tradeoff between floorplan location and voltage drop.

Abstract: An auto-termination method and apparatus for use with either active high or active low terminators are disclosed. The method includes the steps of (a) forcing a terminator to a first state by impressing a first voltage upon an input of the terminator; (b) determining, from the first voltage, a second voltage that when applied to the input of the terminator places the terminator in a second state; and (c) selectively forcing the terminator to the second state by impressing the second voltage upon the input of the terminator. The apparatus includes a terminator and a controller. The terminator is coupled to the bus and includes an input that is coupled to a first voltage that forces the terminator to a first state.

Abstract: A method and apparatus for writing data to a storage device such as a hard disk drive in which two write commands from an initiator are processed as a single command at the storage device. A first request is received from a small computer systems interface (SCSI) bus to write a first set of data to a storage device. The first set of data is transferred to memory for temporary storage prior to transfer to the storage device. Thereafter, a second write request is received to write a second set of data to the storage device in which the write request includes a logical block address. An ending logical block address determined after transferring the first set of data is compared to the logical block address of the second request to determine whether the second set of data can be written to the storage device along with the first set of data as a single write operation based on the comparison of the logical block address of the second request and the ending logical block address.

Abstract: A logic-cell model accounts for nonlinear effects in determining propagation delay, thereby providing improved accuracy as compared to existing models, particularly when rise/fall times exceed several nanoseconds. Given a logic cell of the type wherein delay is a function of rise/fall time (TRL) and load capacitance (CL), the method involves choosing a plurality of discrete simulation points associated with the delay, each point also being a function of TRF and CL, after which the delay is determined in accordance with the chosen simulation points. One or more of the simulation points are preferably chosen in conjunction with both the linear and nonlinear regions of the TRL/CL space to ensure accuracy for a wide range of TRL and/or CL values. In the event of an identifiable or discontinuous transition between the linear and nonlinear regions, a discrete simulation point is also chosen with respect to the transition area.

Abstract: A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.

Abstract: An integrated circuit having a DC current test function operates at a core supply voltage and interfaces at an input-output (I/O) supply voltage. The I/O supply voltage is greater than the core supply voltage. The integrated circuit includes a buffer, a voltage level shifting circuit and a pull-up circuit. The buffer is coupled between a core terminal and a pad terminal. The pad terminal has a voltage swing which is substantially equal to the I/O supply voltage. The voltage level shifting circuit has a test signal input with a voltage swing substantially equal to the core supply voltage and a test signal output with a voltage swing from the I/O supply voltage to a selected bias voltage. The pull-up circuit is coupled to the pad terminal and has a control terminal coupled to the test signal output.

Abstract: A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Abstract: Apparatus and method for forming silicon dioxide films on semiconductors using oxygen plasma and TEOS includes mass spectrometric and/or optical emission spectrometric analyses of the plasma to control selected operating parameters in order to increase the ratio of molecular oxygen cations to atomic oxygen cations present in the plasma, thereby to reduce the resultant concentrations of carbon and hydrogen atoms contained in the oxide film thus formed. Oxide films of high dielectric properties are identified as having concentrations of carbon not greater than about 1 ppm, and hydrogen not greater than about 10E13 cm-3. Bond energies among atoms of carbon, oxygen, hydrogen, and silicon in TEOS are analyzed to indicate requisite operational parameters in a plasma including oxygen and TEOS for forming oxide films of superior dielectric properties.

Abstract: A differential output circuit has first and second output lines and an output impedance connected between the first and second lines. The output impedance includes an active device (e.g., a field effect transistor) having a control input for receiving a control signal value for controlling the impedance value of the active device. A bias circuit is responsive to a reference impedance element for generating the control signal value for controlling the impedance value of the active device. An output driver stage is connected to the first and second output lines for supplying first and second differential driven output signals to the first and second output lines, respectively. An integrated circuit can include a number of differential output circuits and a common bias circuit responsive to a single reference impedance element for generating the control signal value for controlling the impedance value of each active device.

Abstract: A digital network system accommodates a plurality of network protocols. The digital network system includes a backbone bus for communicating digital information. A first switching interface unit is coupled to the backbone bus and has at least one port connected to a first network. A second switching interface unit is also coupled to the backbone bus and has at least one port connected to a second network. The first and second interface units transferring digital information in first and second network protocols, respectively. First and second memories are coupled to the backbone bus and to the first and second switching interface units, respectively, and store digital information to be transferred between the switching interface units via the backbone bus. The first switching interface unit and the first memory are formed on a single substrate, and the second switching interface unit and the second memory are formed on a single substrate.

Abstract: The subject method comprises providing a semiconductor package and a semiconductor package substrate having respective first and second major sides. A stiffener member, which is attachable to the semiconductor package substrate, is employed for purposes of minimizing package warpage. The stiffener member is attached to the semiconductor package substrate to provide the requisite support for the semiconductor package substrate during the assembly process and thereby counteract the sources of the package warpage problem. A protective outer layer can be optionally added to the subject system.

Abstract: A random access memory has an access time which is longer than the period of read input signals, for example digital video data signals, such that it cannot respond directly to the input signals. The memory has two read address inputs and two outputs which are arranged as separate channels, each of which can access any location in the memory. The access time of the memory is shorter than two input signal periods. The input signals are applied alternatingly to the read address inputs, and output signals constituted by data stored at addresses corresponding to the input signals are produced at the memory outputs by an arrangement of clocked latches such that, although two input signal periods are used for accessing each memory location, the alternating accessing using two channels enables the memory to produce output signals having the same period (at the same frequency) as the input signals.

Abstract: A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described.

Abstract: A method is provided for using twisted bit or signal lines and routing restrictions on the logic signal lines to pass logic signals over an on-chip memory. In one embodiment, the memory array includes complementary bitlines which are provided with periodic twists, and the logic signal routing is restricted in that logic signals are either routed perpendicular to the bit lines, or they are routed parallel to the bit lines in such a manner as to ensure equal coupling to both B and B'. The equal coupling is provided by either restricting the length of the logic signal line segment to an integral number of twist wavelengths, or by placing the logic signal line segment so that its midpoint rests on a twist centerline. In another embodiment, the memory array includes bitlines running parallel to a bitline axis, and complementary logic signal lines are routed in pairs.

Abstract: An output drive circuit enables both 5V and 3V devices to be connected to the same bus, without exposing the 3V devices to damage from the 5V signals on the bus. The 3V devices utilize 3V output drives that are tolerant of the 5V signals on the bus. The tolerance is achieved by a circuit design which adjusts internal voltages depending upon the external voltage on the bus. The internal voltage adjustments prevent transistor voltage limits from being exceeded and hence prevent damage from occurring.