Abstract: A method for hardening of gate oxide without forming low dopant concentration regions at the gate oxide-polysilicon interface is described. Polysilicon is deposited onto gate oxide followed by nitrogen implantation and annealing. At this point nitrogen concentration peaks exist at the gate oxide interfaces with the single crystal substrate and the polysilicon gate electrode. This effectively hardens the gate oxide. A third polysilicon gate electrode exists in the bulk of the polysilicon gate electrode. In the described process the region of the polysilicon layer that contains the nitrogen concentration peak is removed. An electronically active dopant may then be implanted. Alternatively, a fresh polysilicon layer may then be deposited followed by implantation of an electronically active dopant. Thus, the method of the invention avoids retardation of electronically active dopant diffusion.

Abstract: A single chip network interface apparatus includes a host interface circuit for communication with a host system bus, a network interface circuit for interfacing with a network bus, a dual port RAM coupled to the host interface circuit and also coupled to the network interface circuit, and a processor coupled to the dual port ram for converting packets of information between network protocol format and a format suitable for the host system bus.

Abstract: Methods and associated apparatus for improving the fairness of bus allocation in association with standard SCSI bus arbitration. The present invention provide a plurality of time slots each of which define a delay period following the SCSI specified minimum period before arbitration is allowed to begin. Each device which requires arbitration on the SCSI bus pseudo-randomly selects one of the time slots before attempting SCSI bus arbitration. The device then delays the associated period of time before commencing SCSI bus arbitration. At any time before the end of the delay period, if the device senses that the SCSI bus has again become busy, then the device has already lost the arbitration without actually competing therefore. A second device, having selected a time slot with a shorter delay period, has won control of the SCSI bus before the first device attempted arbitration. The time slots are selected with a probability associated with each slot.

Abstract: A process of forming a tungsten contact plug, on an integrated circuit (IC), that is substantially free of seam formation is described. The process includes forming a dielectric layer on a surface of a substrate, forming a via in the dielectric layer, blanket depositing a first bulk layer of tungsten on the dielectric layer and partially filling the via, blanket depositing an amorphous or a microcrystalline layer of tungsten over the first bulk layer of tungsten such that growth of tungsten grains inside the via is effectively inhibited, and blanket depositing a second bulk layer of tungsten on the amorphous or microcrystalline layer.

Abstract: A bus bridge circuit having an internal loopback capability involving a shared memory interface integrated therewith. The bridge circuit of the present invention includes a primary PCI interface, a secondary PCI interface, and a shared memory interface. Transfer between the primary and secondary interfaces may proceed in parallel with transfers between the secondary interface and the shared memory interface. A single master device on the primary bus may perform loopback testing of the bridge circuit by directing downstream transactions between the primary interface and the shared memory interface via the secondary interface. Configuration parameters of the bridge circuit permit the address range of the shared memory interface to temporarily overlap the address range of the secondary interface. The primary bus master device configures such an overlapping range and directs transactions to the secondary interface in the overlapping address range.

Abstract: A analog-to-digital conversion apparatus and method for mobile communication devices are disclosed by the present invention. Because the conventional CMOS process does not allow for high order anti-aliasing circuits to be fabricated with digital circuits on the same chip, a new apparatus had to be developed to use low order anti-aliasing filters for the analog-to-digital conversion. The apparatus of the present invention includes a low order anti-aliasing circuit, a delta-sigma converter, and post-conversion filters. The post conversion filters include a decimation circuit, a droop correction filter, and an offset adjust circuit. In this implementation, a low order analog anti-aliasing filter can be used along with a delta-sigma converter and post-conversion filters to eliminate the need for high order analog anti-aliasing filters. Another aspect of the present invention is the duplication of the circuits to process the incoming signals. The duplicate circuit is fed a null signal to process the noise only.

Abstract: A method of sorting dies found on wafers is disclosed. Each wafer is part of a set of wafers and the sorting rejects some of the dies. The method first selects an acceptable deviation within an abstract distribution. A respective test parameter is measured and recorded for each die in the set of wafers, and a distribution of the test parameter across the set of wafers is calculated. Based on this distribution and the acceptable deviation, a test parameter limit is set and any dies having a test parameter value greater than the limit are rejected.

Abstract: A structure and method is shown for measuring a plug and interface resistance values of an inter-layer contact structure in a semiconductor device. An inter-layer contact plug interconnects two metal layers in the semiconductor device forming a pair of plug to metal layer interfaces. A conductive trace is formed in an inter-metal dielectric layer between the metal layers, where the conductive trace couples the conductive plug to a pair of externally accessible pads. Each of the metal layers has a pair of pads. Using the pads coupled to the conductive trace, current is forced through each of the plug to metal interfaces and a voltage difference across each interface is measured in order to obtain the resistance of each interface. The total resistance of the inter-layer contact plug is similarly obtained and the resistance of the plug itself is obtained by subtracting the resistance of the two interfaces from the total resistance.

Abstract: In providing security for data within an integrated circuit, a plurality of fusible links are connected in series between a programming input/output pad and the integrated circuit into which protected data is written. The links are provided with separate input/output pads for individually blowing each link. Blowing any fusible link in the series prevents the programming input/output pad from being employed to alter or copy secured data within the integrated circuit. The failure rate of the security feature thus becomes a product of the fallout rates for each individual link, greatly reducing the overall failure rate.

Abstract: A method and apparatus for testing a RAM BIST controller by initializing a RAM behavior model with known fault data, running a RAM BIST controller model along with the RAM behavior model, and then comparing the output of the RAM BIST controller model with the known fault data to determine if there are any differences. A difference will indicate a fault in the RAM behavior model. The accuracy of the RAM BIST controller can then be used to compare the design of the RAM BIST controller with designs for other RAM BIST controllers in order to find the ideal RAM BIST controller for the intended purposes.

Abstract: An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one hole. A system for attaching a heat dissipater to an electronic semiconductor device package, the system comprising: a stiffener of the electronic package comprising at least one hole, wherein the stiffener is attachable to the electronic package; a heat dissipater comprising at least one pin, wherein the pin is engagable with the hole.

Abstract: A processor for a data-processing system is provided with a dynamically reconfigurable multistage pipeline which permits the execution of more than one instruction set by the processor utilizing the same instruction decoding circuitry and instruction execution control logic circuitry. In one embodiment, the pipeline includes an instruction fetch stage, an instruction conversion stage, an instruction decode stage, and a multiplexer which is used to switch the instruction conversion stage into and out of the pipeline between the instruction fetch stage and the instruction decode stage, even while instructions continue to be executed by the pipeline. The multiplexer operates under control of the instruction decode stage and may be set in response to decoded instructions. The instruction fetch stage is coupled to a bus to retrieve an instruction at a location specified by a program counter.

Abstract: An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.

Abstract: A phase locked loop includes a differential charge pump to cancel static phase error and reduce sensitivity to noise. The differential charge pump comprises two substantially identical single-ended charge pumps so that under locked condition, changes in voltage at the charge pumps' output terminals are substantially identical, thereby maintaining a substantially constant difference between the charge pumps' output voltage. A differential input voltage-controlled oscillator receives the output of the differential charge pump and generates a clock signal with a frequency proportional to the voltage difference output by the differential charge pump. A common mode bias circuit adjusts the common mode voltage output by the differential charge pump to optimize the voltage swing available at the differential charge pump's output terminals.

Abstract: A leadframe having individual bond fingers incorporating two or more alternate bonding areas. In one embodiment, conventional bond fingers having bonding areas in an outer row are augmented to include an additional conductive trace or intermediate portion terminating in a bonding area that is in general alignment with an inner row of bonding areas. Likewise, bond fingers having bonding areas in an inner row are enlarged to include an alternate bonding area that is in general alignment with the outer row of bonding areas. In another embodiment, bond fingers are arranged to provide multiple rows of closely-spaced staggered bonding areas to reduce bonding pitches. By providing alternate bonding areas in individual bond fingers, the manufacturing rules addressing staggered bond wire placement can be followed more readily, while simultaneously permitting the most convenient bond fingers to be utilized.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate and a heat spreader. The chip includes multiple I/O pads preferably arranged in a two-dimensional array on an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The substrate maintains its substantially planar shape during C4 heating. The heat spreader is thermally conductive and preferably dimensioned to substantially cover the upper surface of the substrate. An underside surface of the heat spreader includes a cavity dimensioned to receive the chip and multiple pins extending outwardly therefrom. The substrate includes multiple holes adapted to receive the pins of the heat spreader.

Abstract: A circuit and method are shown for a continuously adjustable delay circuit. The present invention utilizes two signal delay paths controlled by a tuning signal wherein each delay path receives a reference signal. The first delay path delays the reference signal in response to the tuning signal in a manner that is complementary to the manner in which the second delay path delays the reference signal in response to the tuning signal. By selecting one of the signal output by the first delay path and the signal output by the second delay path and switching between the two signals at a point when the two signals are separated by a period of the reference signal, a delay of the reference signal can be continuously adjusted.

Abstract: Digital filtration is accomplished by splitting the incoming signal into phases. Each phase is then converted into a weighted sum reflecting the design of a prototype filter. Then the data is again split into phases at which time specific points may be interpolated and the data accumulated until a filtered signal has resulted. All of the steps can be easily modified after manufacture so that the filtration can handle variable bandwidth systems at low data rates, as well as implement a wide variety of filtering structures.

Abstract: An electronic system such as a Board-Level-Product (BLP) includes at least one integrated circuit device which is mounted on a circuit board. Each integrated circuit device includes a thin dielectric substrate bearing a plurality of conductive leads and has a hole circumscribed by the substrate in which is positioned a die having pads that are bonded to ends of leads carried by the substrate and projecting into the hole for contact with the die pads. The leads include free outer ends that project laterally outwardly and downwardly away from the plane of the substrate for connection to contact pads on the circuit board.

Abstract: A semiconductor device package is presented having signal traces interposed between power and ground conductors in order to form stripline transmission lines. The semiconductor device package includes a substrate having a die area defined upon an upper surface. The die area is dimensioned to receive the integrated circuit. A first planar conductive layer formed upon the upper surface includes a first set of bonding pads and a set of conductive traces. Members of the first set of bonding pads are arranged upon the upper surface proximate the die area, and are used to make electrical connections to the integrated circuit. Members of the set of conductive traces are connected between one of two polarities of a power supply and corresponding members of the first set of bonding pads, and function as reference planes for underlying signal traces. A second planar conductive layer is positioned between the first planar conductive layer and an underside surface of the substrate.