Abstract: To provide high purity gases to manufacturing tools, a gas isolation box is employed which is formed of stainless steel and includes vertical slots for receiving gas stick carrier cards. Gas sticks include required valves, gauges, and regulators rigidly mounted on stainless steel carrier cards, leak tested and labeled. The carrier cards with the rigidly mounted, leak tested gas sticks are slid into the vertical slots of the gas isolation box. Only two connections are then required to complete to gas lines, reducing the potential for flexing of high purity gas lines during installation.

Abstract: A method of setting a plurality of addresses is disclosed. The method includes the step of setting a first module identifier for a first device module. The method further includes the step of setting a first address for a first device, said first address comprising an upper section and a lower section. The method also includes the step of setting a second address for a second device, said second address comprising an upper section and a lower section, wherein the step of setting the first address for the first device includes the steps of setting the upper section of the first address to the first module identifier, and setting the lower section of the first address to a first value; and wherein the step of setting the second address for the second device includes the steps of setting the upper section of the second address to a second value, and setting the lower section of the second address to the first module identifier.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage (or after storage, if desired) in the Vector FIFO buffer when error concealment is performed.

Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: An on-chip driver is described for applications voltage output signals are desired from a digital sub-micron CMOS integrated circuit. The driver includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output-up down and the level shifter. The output pull-down is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level of about 0 volts when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up which pulls the output of the driver to a high voltage level of 2.5 volts or greater when the digital CMOS input is at a high logic state.

Abstract: A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.

Abstract: A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Abstract: A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.

Abstract: A cell placement for an integrated circuit chip comprises a large number of cells allocated to respective locations on the surface of the chip. The placement is divided into switch boxes that surround the cell locations respectively. A bounding box is constructed around each net of a netlist for the placement. A congestion factor is computed for each switch box as being equal to the number of bounding boxes that overlap the respective switch box. A cost factor for the placement and associated netlist is computed as the maximum value, average value, sum of squares or other function of the congestion factors. The individual congestion factor computation can be modified to require that a pin of a net of one of the bounding boxes overlap or be within a predetermined distance of a switch box in order for the congestion factor to be computed as the sum of the overlapping bounding boxes in order to localize and increase the accuracy of the cost factor estimation.

Abstract: A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a-high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A semiconductor device package containing a semiconductor die uses a platform mounted on an active face of the die. The platform electrically connects to at least one bond pad on the die. A package lid electrically connects to the platform on the die and a package case connection. The package case connection is also electrically connected to at least one external connector on the package. The platform and package lid thereby connect the at least one bond pad on the die to the at least one external connector on the package. Using the platform and lid for electrical connections from the semiconductor die bond pads to the external package connector reduce the number of bond fingers required to surround the perimeter of the die. The package lid and platform may, for example, be used for ground or power connections to the die bond pads.

Abstract: The present invention includes an apparatus for supporting a device in a computer comprising a base, preferably juxtaposed to a connector, and a ledge extending from the base section. The base preferably defines a channel to fit the apparatus to the connector. The channel can be defined by arms that are included in the base. At least one support strut extends between the base and the ledge. A disk drive is supported by the apparatus. The disk drive is seated against the ledge to provide support and to attenuate vibrations caused by the rotating disk. Preferably, the apparatus is seated against a motherboard so that the connector does not bear the weight of the disk drive. One modification of the present invention integrates the connector and the apparatus.

Abstract: According to one aspect of the invention, a semiconductor package is provided including a package substrate having an upper surface and a lower surface, wherein electrical contacts on the lower surface of the substrate are coupled to corresponding electrical contacts on a printed circuit board by a plurality of solder balls; a semiconductor die having a non-active surface and an active surface, wherein the active surface is electrically coupled to the upper surface of the package substrate by a plurality of solder bumps; and an integrated heat spreader and ring stiffener coupled with the non-active surface of the semiconductor die by a phase change material which is retained by a miniature dam ring while in a liquid state, wherein heat generated by the die is transferred to the heat spreader, and wherein the heat spreader has a protrusion formed thereon which matches the outermost size of the die.

Abstract: Provided is a single-piece integrated heat spreader/stiffener which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The heat spreader/stiffener is equipped with a plurality of apertures to provide access to the top surface of the die for adhesive to bond the heat spreader/stiffener to the die, and to its perimeter to provide access for dispensation of underfill material between the die and the substrate. Once the adhesive and underfill materials are in place, the adhesive and underfill resins are cured by heating.

Abstract: A process for implementation on a programmed digital computer includes providing a placement of clusters of cells which are assigned to regions on an integrated circuit chip, and combining the regions to form region groups. The region groups collectively constitute a "jiggle" which resembles a sieve. The clusters in each region group are re-assigned to the regions in the region group. The regions are recombined to form different region groups (a different jiggle), and the clusters in each different region group are re-assigned to the regions in the different region group. These steps are repeated using at least two, preferably four different jiggles, until an end criterion is reached. Then, the regions and clusters are hierarchically subdivided, and the process is repeated for each hierarchical level until the clusters have been reduced to individual cells.

Abstract: A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample subset, and a parameter calculation unit which computes one or more statistical parameters from the failure times. These statistical parameters are then used to determine a refresh pause time which is used in a data retention test of the memory array. The testing method may be performed when power is applied to the memory device. Thus, the BIST method may provide for the accurate detection of memory faults in the memory array at any power-up temperature. In addition, the testing method may be performed after the memory array attains an operational temperature, or in response to an operating system command.

Abstract: A machine-independent operating environment, method and storage medium embodying machine-code usable by a computer system for exchanging design information between a plurality of computer-aided design tools. A set of data format objects are provided for exchanging the design information between each computer aided-design tool. An accessing method is provided for enabling each computer-aided design tool to store the design information into and retrieve the design information from an associated data format object. An archiving method is provided for enabling the computer system to write the data format objects storing the design information onto and read the data format objects storing the design information from a storage device interconnected with the computer system using each associated data format object. Preferably, each computer-aided design tool is expressed in machine-portable object code which is executed by a virtual machine on the computer system.

Abstract: One aspect of the invention relates to a method for providing a semiconductor package with a thermally conductive coating, the semiconductor package including a package substrate having a plurality of electrically conductive traces formed thereon, an upper surface and a lower surface, the lower surface having a plurality of contacts for providing electrical connection between the conductive traces formed on the package substrate and a plurality of conductive traces formed on a printed circuit board, and a semiconductor die mounted to the upper surface to the package substrate, the semiconductor die having a plurality of bond pads formed thereon which are electrically connected to the conductive traces formed on the package substrate. In one embodiment, the method includes the steps of depositing a coating on the upper surface of the package substrate and the coating includes a diamond film or diamond particles.

Abstract: A serial data interface device is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers, etc. The interface includes first and second ports capable of receiving and transmitting information to respective electronic devices, and first and second storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first and second ports and are coupled to another electronic device. Included in each storage device is a main memory that is coupled to at least one of the electronic devices and at least one of the ports. A control memory that is coupled to the main memory is also included, along with a main memory arbiter that is coupled to the control memory and the main memory. Further included is a buffer allocation control that is coupled to the at least one electronic device and at least one of the ports.