Abstract: A redundant storage control module (also referred to as RDAC or multi-active controller) maintains a queue of pending I/O requests sent for processing via a first asynchronously operating I/O path. In the event of failure of the first asynchronously operating I/O path, the controller restarts the entire queue of pending I/O requests to a second I/O path without waiting for each request to individually fail from the first path. Some prior techniques required the RDAC module to await failure of each I/O request sent to the failed first I/O path before restarting each failed request on the secondary I/O path. Such techniques greatly extend the total time required to restart all operations sent to a failed I/O path, by awaiting the failure of all I/O requests previously sent to the first I/O path.

Abstract: A conveying assembly in a conditioning sub-assembly for conveying a conditioning surface to a polishing pad during conditioning is described. The conveying assembly includes an arm and a guiding component connected to the arm and adapted to guide the conditioning surface about the conveying assembly, thereby allowing another area of the conditioning surface to advance and become available for conditioning.

Abstract: A data processing system that includes an improved architecture for providing hot spare storage devices. Specifically, the data processing includes a bus that is connected to one or more computer systems and a number of storage subsystems. Each storage subsystem includes storage devices and a controller. The controller in a storage subsystem provides the connection to the bus and an interface for controlling data transfers to and from the storage device. A backup storage system is connected to the bus. The data processing system also includes a detection means for detecting a failure of a storage device within one of the plurality of storage subsystems and a backup means for using the backup storage device to replace the failed storage device.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator modified to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Abstract: Generally, a method checks the error signals of the interleaves to determine if the number of error bursts, burst error lengths or burst size is exceeded. These values are predetermined limits. To this end, the present invention tracks the number of errors and attempts to "fit" the errors in the programmed parameters of the burst size and burst limit values, such as illustrated above. If there is no fit, then an error signal is provided by burst limit checker.

Abstract: A method and apparatus for controlling access to a bus. A target having a period of unavailability is identified. A master device requesting access to the bus to initiate a data transfer between the master device and the target device also is identified. The master device is denied access to the bus for a delay period in response to the master device attempting to retry a data transfer with the target device, wherein the delay period is a time period after which the target device becomes available for additional transfers, wherein the bus is available to other master devices during the delay period.

Abstract: An end effector to facilitate conditioning of a surface of a polishing pad used in chemical-mechanical polishing of an substrate surface is described. The end effector includes a rigid body including a contact surface capable of being attached to a conditioning disk and having a predetermined non-planar region that is adapted to at least one of (i) effectively maintain a non-planar area on the surface of the polishing pad and (ii) shape the polishing pad, when the end effector is employed to condition the polishing pad.

Abstract: A novel semiconductor fabrication chamber includes a quartz vessel and a metal vessel with a resilient sealing member disposed between the quartz and metal vessels to define a vacuum chamber, along with a cooling assembly mounted on a quartz flange extending around the perimeter of the quartz vessel. A liquid or gaseous cooling medium is passed through the cooling assembly to reduce the operating temperature of a portion of the resilient sealing member in contact with the quartz flange during semiconductor fabrication processing so as to extend the useful life of the sealing member. The cooling assembly is secured to the quartz flange using a plurality of clamping fixtures for easy installation and retrofitting.

Abstract: An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one clip. A system for attaching a heat sink to an electronic semiconductor device package, the system comprising: a stiffener of the electronic package which is attachable to the electronic package; and at least one clip that is integral with the stiffener and secures the heat sink to the stiffener. A method of detachably attaching a heat sink to an electronic semiconductor device package, the method comprising: attaching a stiffener to the package, wherein the stiffener comprises at least one clip; positioning a heat sink adjacent the stiffener; and engaging the clip with the heat sink, wherein the heat sink is secured to the stiffener by the clip.

Abstract: An recovery circuit is described for recovering data from serially transmitted digital signals wherein a very long hold time and infinite phase range is desired. The recovery circuit includes a variable delay line, a data tracking phase-locked loop (PLL), a clock tracking phase-locked loop, a phase sensor, and a switch. The variable delay line is responsive to a feedback signal and a clock signal for generating a first delayed phase-locked signal. The data tracking phase-locked loop is responsive to the first delayed phase-locked signal and a data signal for producing a data phase error signal. Similarly, the clock tracking phase-locked loop is responsive to the clock signal for providing a second delayed phase-locked signal. Responsive to both of the delayed phase-locked signals is the phase sensor which provides a select output signal when the phase-locked signals are in phase with each other.

Abstract: A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is controlled by a main memory controller circuit. One or more bus bridge circuits adapt the signals from the bus architecture used by the legacy systems to the high speed cache memory. The bus bridge circuits each adapt, for example, a PCI bus used for a particular cache access purpose to the signal standards of an intermediate shared memory bus. The main memory controller circuit adapts the signals applied to the intermediate shared memory bus to the high speed cache memory bus. The hierarchical bus architecture permits older "legacy" control methods and structures to be easily adapted to newer cache memory architectures.

Abstract: A RAID storage system which attempts to balance the I/O workload between multiple redundant array controllers is presented. The RAID storage system of the invention utilizes a plurality of redundant array controllers which require static ownership of storage devices for WRITE access requests to the same redundancy parity group. Accordingly, a plurality of storage devices are provided in the system, each of which is owned by one of the redundant array controllers. Each storage device is coupled to both its owner controller and at least one other array controller. Each array controller coupled to a storage device has the ability to read and write data from and to the storage device. Each array controller has a processing queue from which pending read and write access requests are removed and then processed one at a time by the controller. A host computer is provided for dispatching read and write access requests to the redundant array controllers.

Abstract: Decimation and interpolation of pulse code modulated (PCM) digital audio samples is performed by periodically skipping or repeating a single PCM value. A random access memory (RAM) acting as a FIFO buffer memory outputs PCM samples in response to an address output from a counter. A predetermined number of PCM samples are output from the FIFO buffer by incrementing the counter at a constant rate. Decimation is performed by doubling the incrementing rate for one read interval, and interpolation is performed by halting the incrementing for one read interval. Modifying the incrementing rate of the counter provides an economical implementation of decimation and interpolation without introducing distortion.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions high angle ion implantation are required.

Abstract: Special probe pads are formed within the core of an integrated circuit, such as an ASIC, to provide direct access to internal circuitry for conducting failure analysis. For example, internal probe pads can be provided around an embedded RAM core for bit mapping the RAM core if necessary. An improved probe card is described to provide for accessing these internal probe pads using automated probing machines. The internal probe pads, preferably smaller in size than wire bonding pads, are located in available interstices on the die, preferably without increasing silicon area. Multiplexers can be used to isolate these probe pads during normal operation of the integrated circuit.

Abstract: A way of designing CPU's and computational units in an integrated circuit so that the computational unit can be designed and connected to the CPU in a modular manner. The computational unit designed for one application can be redesigned for another application without requiring a change in the CPU. The CPU has an instruction register, a first decoder connected to the instruction register to decode instruction words within a predefined set of instructions, an ALU, and buses which move operand data into the ALU and results data from the ALU. The ALU operates and the buses function responsive to the first decoder. The computational unit has an execution unit connected in parallel with the ALU to the buses, and a second decoder connected to the instruction register. The second decoder decodes only a predetermined portion of an instruction word in the instruction register when the instruction word is not in the predefined set of instructions. The execution unit operates responsive to the second decoder.

Abstract: A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.

Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract: An entity relationship diagram for a relational database is generated from introspection of the relational database to determine which entities should be included within a specific table to be displayed. Tables within the entity relationship diagram are displayed with icons hyperlinked to other portions or displays of the entity relationship diagram. A trigger icon links the displayed table to a display of the trigger information for the displayed table. A primary key icon indicates which column of the displayed table is utilized as the primary key for the displayed table, while a foreign key icon links the displayed table to a display of another table in the entity relationship diagram containing the foreign key. Dashed or dotted lines and dot or diamond terminators associated with the foreign key icon described the relationship between the displayed table and the linked table. A constraint icon links the displayed table to a display of the constraint information for an entity.

Abstract: An etch process selective to cobalt silicide is described for the selective removal of titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, remaining after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide. The first step comprises contacting the substrate with an aqueous mixture of ammonium hydroxide (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) to selectively remove any titanium and/or titanium nitride in preference to the removal of cobalt silicide. The second step comprises contacting the substrate with an aqueous mixture of phosphoric acid (H.sub.3 PO.sub.4), acetic acid (CH.sub.3 COOH), and nitric acid (HNO.sub.3) to selectively remove cobalt and cobalt reaction products (other than cobalt silicide) in preference to the removal of cobalt silicide.