Abstract: Methods and associated apparatus for coordinating file lock requests from a cluster of attached host computer systems within I/O controllers (e.g., intelligent I/O adapters) attached to a storage subsystem. The I/O controllers, operable in accordance with the methods of the present invention, includes semaphore tables used to provide temporary exclusive access to an identified portion of an identified file. The host systems request the temporary exclusive access of a file through the I/O controllers rather than over slower network communication media and protocols as is known in the art. The I/O controllers then manages a plurality of competing lock requests to provide mutual exclusivity of the file access. The file lock management is therefore managed over the higher bandwidth storage interface channels of the host systems and without the generalized network protocols burdening the lock management process and the host system CPUs.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions to a polishing pad are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a surface of a semiconductor wafer includes a polishing pad with a first surface and a second surface. The first surface of the polishing pad is arranged to contact the surface of the semiconductor wafer in order to polish the surface of the semiconductor wafer. The apparatus also includes a mechanism which is used to apply a non-uniform pressure distribution over the second surface of the polishing pad, wherein applying the non-uniform pressure distribution to the polishing pad facilitates evenly polishing the surface of the semiconductor wafer. In one embodiment, the mechanism for applying the non-uniform pressure distribution to the polishing pad is an air bladder arrangement.

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.

Abstract: A video decoder which uses a dynamic memory allocation scheme having a synchronization counter for decoder-display synchronization. The synchronization counter advantageously allows for graceful recovery from error conditions in which the decoding portion of the video decoder falls behind the display portion of the video decoder. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Abstract: Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.

Abstract: According to the present invention, a single chip semiconductor devices is provided. In one version of the invention, a single chip CMOS technology architecture is used to implement all or various combinations of baseband radio transmission, baseband interfaces and filtering, source coding, source interfaces and filtering, control and supervision, power and clock management, keyboard and display drivers, memory management and code compaction, digital signal processing ("DSP") and DSP memory and radio interface functions.

Abstract: The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.

Abstract: In a multiprocessor data processing system including at least one main processor and one sub-processor utilizing a shared queue, queue integrity is maintained by associating a semaphore with each queue entry to indicate ownership of that queue entry. Ownership of a queue entry is checked by a processor attempting to post to the queue entry. Upon determining that the queue entry is available to the processor, the queue entry is loaded by an atomic write operation, ownership of the queue entry transferred to another processor, and the other processor may be alerted of the post to the queue. The other processor maintains ownership of the queue entry until the other processor has read and saved the data from the queue entry. Items may thus be posted to the queue and cleared from the queue by a processor independent of the state of the other processor.

Abstract: A Tape-Automated-Bonding (TAB) package includes a resilient polyimide layer that supports a metal leadframe. A microelectronic circuit die is mounted in a hole in the polyimide layer and interconnected with inner leads of the leadframe. The TAB package is adhered to a support member having spacers that abut against the surface of a printed circuit board (PCB) on which the package is to be mounted and provide a predetermined spacing between the leadframe and the surface. Outer leads that protrude from the leadframe are bent into a shape so as extend, in their free state, toward the surface at least as far as the spacers. The package and support member assembly is placed on the PCB surface, and the combination of the weight of the assembly, the resilience of the leads and the preset standoff height enable the leads to resiliently deform so that the spacers abut against the surface and the leads conformably engage with the surface for soldering or other ohmic connection to conjugate bonding pads on the surface.

Abstract: A linear interpolator for determining a weighted average between first and second terms having first and second weights, respectively. The linear interpolator includes a first multiplier for multiplying the first term and an inverse of the second weight to produce a first set of partial products, a second multiplier for multiplying the second term and the second weight to produce a second set of partial products, a carry-save addition ("CSA") tree and an adder. The CSA tree and adder combine the first set of partial products, the second set of partial products, and the first term to produce the weighted average. In another embodiment, the linear interpolator includes a plurality of multiplexers (muxes), the number of muxes being equal to the bit width of the second weight. Each mux selects between the first and second term, depending on whether the corresponding bit of the weight is a zero or one, to produce a plurality of partial products.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage in the Vector FIFO buffer when it is desired to soft-mute an audio output of the decoder.

Abstract: This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.

Abstract: A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Abstract: A differential current mode driver is provided with output source and sink currents that remain nearly equal in magnitude and opposite in direction throughout normal, power-down, and power-up modes of operation. Three time constants are employed to regulate these different modes of operation. The differential current mode driver includes a first time constant to stabilize the output source and sink currents during the on-state, a second time constant to control the transition from the on-state to tristate, and a third time constant to control the transition from tristate to the on-state, all the while maintaining equal source and sink currents.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: A method for transferring data from a first device to a second device where the second device has a main data processor and a secondary processor associated therewith. The method includes the steps of (1) transferring a data stream having a control portion and a data portion from the first device to the second device, and (2) processing the data portion with the secondary processor in accordance with the control portion without interrupting the main data processor. A multi-controller apparatus which is useful for practicing the method is also disclosed.