Abstract: A CMOS-technology, DRAM integrated circuit includes paired P-type and N-type wells in a substrate, which wells are fabricated using a self-aligning methodology. Similarly, FET's of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning methodology to provide FET's of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. The DRAM includes a multitude of capacitor structures formed atop the FET's of the substrate, and plural layers of insulative dielectric with embedded bit and word traces providing for connection of the multitude of memory cells of the DRAM to external circuitry.

Abstract: A Multi-Chip-Module (MCM) microcircuit comprises a substrate, a plurality of integrated circuit processors mounted on the substrate, and an Advanced Programmable Interrupt Controller (APIC) system for distributing interrupts to the processors. The APIC system comprises a plurality of local units for prioritizing and passing interrupts to the processors respectively, and an Input/Output (I/O) unit for feeding interrupts to processors to which the interrupts are addressed. Electrical conductor patterns are formed on and between dielectric layers of the substrate for interconnecting the processors, the local units and the I/O unit.

Abstract: Methods of etching optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed.

Abstract: A Tape-Automated-Bonding (TAB) package includes a resilient polyimide layer that supports a metal leadframe. A microelectronic circuit die is mounted in a hole in the polyimide layer and interconnected with inner leads of the leadframe. The TAB package is adhered to a support member having spacers that abut against the surface of a printed circuit board (PCB) on which the package is to be mounted and provide a predetermined spacing between the leadframe and the surface. Outer leads that protrude from the leadframe are bent into a shape so as extend, in their free state, toward the surface at least as far as the spacers. The package and support member assembly is placed on the PCB surface, and the combination of the weight of the assembly, the resilience of the leads and the preset standoff height enable the leads to resiliently deform so that the spacers abut against the surface and the leads conformably engage with the surface for soldering or other ohmic connection to conjugate bonding pads on the surface.

Abstract: System and method for optimizing the structure of a transistor to withstand electrostatic discharge by quantitatively evaluating the amount of electrostatic discharge that integrated circuit field effect transistors may endure before material damage results thereto. The system and method utilizes a plurality of test devices, each having certain differences in structure, which are fabricated onto a common integrated circuit substrate for contemporaneous testing of each device under controlled quantitative conditions. The test results may be organized into a "matrix experiment". A matrix experiment is a set of experiments where the settings or values of several product or process parameters to be studied are changed from one experiment to another. An orthogonal matrix array may be utilized to enhance the reliability of the data analysis, and may effectively reduce the number of experiments necessary to establish a reliable conclusion from the limited number of tests performed.

Abstract: Remote electrical contacts for a semiconductor are produced by depositing a polysilicon layer over the entire surface of a semiconductor device and removing a portion of the polysilicon layer by chemi-mechanical polishing. The resulting structure is thereby provided with electrically isolated areas of polysilicon which constitute remote electrical contacts for the semiconductor device. The polysilicon layer or the isolated areas of polysilicon can be salicided to provide very low resistivity. Either the polysilicon layer or the salicide layer can be subjected to ion implantation to provide LDD regions.

Abstract: A semiconductor device package for one or more semiconductor dice uses a package substrate having one pair of biplanar conductive planes and another pair of biplanar conductive planes. The pairs of planes are positioned in a coplanar relationship between the top traces and the bottom traces. Power may be supplied to die core circuits through one pair of planes and to die input-output circuits through another pair of planes to decouple the core circuits from the input-output circuits and minimize noise induced false switching in either set of circuits. The core circuits and the input-output circuits may be powered by the same power supply or separate power supplies.

Abstract: A process is provided for use with a semiconductor testing apparatus having a vector generator which provides a sequence of vectors to a semiconductor device at a rate responsive to a timeset, a power supply which provides current to the semiconductor device and a current monitor which measures the current provided to the device. In one specific embodiment, the process includes setting the timeset to a first rate, conditioning the device by executing a plurality of vectors at the first rate, setting the timeset to a second rate, the second rate being slower than the first rate, and measuring the quiescent current while the timeset is set to the second rate.

Abstract: A complex, say, N=5 or greater input terminal, mask decoder circuit which is useful in the design of ALUs in microprocessors is presented. The circuit avoids wiring and uses logic gates to make the connections between the input terminals receiving the control bit signals and the output terminals on which the mask signals are generated. This allows the mask decoder circuit to occupy a minimal amount of space on an integrated circuit.

Abstract: An integrated circuit includes a plurality of signal lines, a plurality of pull transistors connected between the signal lines respectively and an electrical potential, and an IDDQ test control for turning on the pull transistors for normal operation, and for turning off the pull transistors for IDDQ testing. The IDDQ test control includes a test signal generator for generating an IDDQ test control signal that turns off the pull transistors, and an IDDQ test signal line that is connected to the test signal generator and to the pull transistors. The pull transistors are designed within a periphery of the circuit, and the IDDQ test signal line forms a ring. The test signal generator includes an external pin, a special buffer, or a boundary scan system including a chain of boundary scan cells and a test access port controller. The test control signal can be generated by one of the boundary scan cells, or by the test access port controller.

Abstract: A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.

Abstract: An electrical circuit and method combine junction field effect transistors (JFET) and metal oxide semiconductor (MOS) circuits in series between V.sub.DD and ground, with a feedback of output voltage to control current from V.sub.DD to ground. The electrical circuit comprises a complementary metal oxide semiconductor (CMOS) inverter circuit with an input and an output, and a JFET having a gate coupled to the CMOS inverter for feedback to control the JFET. The JFET and CMOS circuitry is formed on a common substrate with the JFET gate junction being formed by implanting impurity dopants through a layer of gate oxide.

Abstract: A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the retrieved data values, if necessary, to place them in the proper order for the processing array. The address decoder provides a select value to the select logic and a shift value to the shift network for each cycle. For purposes of horizontal decimation, the pixel values are organized into an even and an odd group, which groups are stored in the memory buffer in two separate regions separated by an address offset K.

Abstract: A polishing pad conditioner has a grid with an abrasive surface for conditioning a polishing pad. Opposite the abrasive side of the grid, there is a back surface, having at least one key way, which extends at least partially into the back surface. A grid holder has a number of keys equal to the number of key ways in the back surface of the grid. The grid holder keys engage the grid key ways, thereby eliminating slippage between the grid and the grid holder. A mechanized arm is attached to the grid holder, and imparts a rotational and translational motion to the grid holder. A magnet may be used as an attachment means between the grid and the grid holder. The key ways of the grid and the keys of the grid holder may be arranged such that the grid holder can only receive the grid with the back surface of the grid facing the grid holder.

Abstract: A computer-based method is provided for determining whether a semi-conductor device conforms to design requirements. In one embodiment, the method is based on data stored in a design database, and an automatic test equipment ("ATE") datalog. In a further embodiment, the method includes generating a requirements datalog responsive to the design database, generating a standard datalog responsive to the automatic test equipment datalog, and generating a conformance indication responsive to the requirements datalog and the standard datalog.

Abstract: A single chip hub for an electronic communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for processing the packets, and a plurality of media access interfaces. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface.

Abstract: An integrated circuit fabrication method and apparatus to improve the design cycle time for implementing an electrical system in silicon. The invention uses predefined core, or cell, patterns to provide some of the functionality for a system design. The cores are interconnected using thick wire conductors and solder bumps so that conductive paths that do not lie within the plane of the substrate of the silicon chip containing the cores are provided. Since the conductive paths do not lie on the process surface of the chip, the topographical design of the chip is not affected by the interconnections. Further, the thick wire conductors result in essentially zero propagation delay so that timing design errors are greatly reduced, or eliminated, in the design cycle. The invention allows for a rapid prototype of the entire design to be produced early in the design cycle. In one embodiment, customer logic is arranged around the periphery of the substrate while the core cells are in the middle of the substrate.

Abstract: A system for designing an integrated circuit with multiple functions is disclosed. The system creates a set of files defining a structure for a plurality of functions existing within one integrated circuit. Floorplanning modifications are then permissible within any functional block, as well as from one functional block to another since the files for each integrated circuit chip are reconfigureable upon modification. The subject invention also provides for floorplanning modifications involving multiple integrated circuit chips wherein any one functional block may be moved from one integrated circuit chip to another to achieve better optimization with less restrictions.

Abstract: A process is disclosed for forming trenches having high surface-area sidewalls with undulating profiles. Such trenches are formed by first implanting multiple vertically separated layers of dopant in a substrate beneath a region where the trench is to be formed. Next, the trench is formed under conditions chosen to selectively attack highly doped substrate regions (i.e., substrate regions where the dopant has been implanted). The resulting trench sidewalls will have undulations corresponding to the positions of the implanted regions. In one case, the implanted layers contain germanium ions, and a trench is aniostropically etched through the layers of germanium. Thereafter, the trench is subjected to oxidizing conditions to form regions of germanium oxide. Finally, the trench is exposed to an aqueous solvent which dissolves germanium oxide, disrupting the silicon lattice, and leaving gaps or undulations in the sidewall.