Abstract: A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.

Abstract: An apparatus for producing a plasma suitable for semiconductor processing at pressures in the low millitorr range. The apparatus includes a vacuum chamber with a dielectric window, a generally planar coil disposed adjacent the window outside the chamber and coupled to an appropriate power source, and a plasma initiator disposed within the chamber. Once the plasma is initiated, the planar coil sustains the plasma by inductive power coupling. In one embodiment the plasma initiator is a secondary electrode disposed within the chamber and coupled to a second RF power source. In an alternative embodiment both the secondary electrode and a target pedestal are coupled to the secondary RF power source through a power splitter. In an alternative embodiment, the plasma initiator is used to ionize a portion of the process gas and provide a plasma that may then inductively couple with the planar coil.

Abstract: A technique is described for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.

Abstract: An integrated circuit is mounted on and interconnected with a circuit board by an array of electrically conductive columns. The assembly is fabricated by initially interconnecting the integrated circuit and the circuit board with an array of reflowable electrically conductive solder balls that correspond to the columns respectively. The circuit board is held with the integrated circuit extending downwardly therefrom. Sufficient heat is applied to cause the solder balls to reflow. The integrated circuit is pulled downwardly away from the circuit board by gravity such that the balls are stretched to form the columns, and the assembly is allowed to cool such that the columns solidify. A fixture may be provided against which the integrated circuit abuts after it has moved away from the circuit board by a predetermined distance such that the columns have a precisely determined height.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. TAB processes are disclosed for cutting, bending and bonding inner and outer portions of selected signal layer traces to respective inner and outer edge portions of the additional conductive layer(s), including a two-stage process of (1) first cutting, bending and tacking the selected traces to the additional layer(s), and then (2) repositioning a bonding tool and securely bonding the selected traces to the additional layer(s). A tool (die pedestal) for aiding in the assembly process is also disclosed.

Abstract: One or two, or more, additional conductive layers, separated from one another (if two or more) and separated from a patterned (signal) conductive layer are formed in a flexible substrate, for mounting a semiconductor die in a semiconductor device assembly. These additional layers are used as separate planes for carrying power and/or ground from outside the assembly to the die, on a separate plane from signals entering or exiting the die. Another aspect of the present invention provides a semiconductor device assembly including a first conductive layer with a plurality of traces formed on an insulating layer, a second conductive layer with an inner edge portion exposed within the central opening in the insulating layer, and a leadframe having a number of leads the inner end of one or more of the leads being electrically connected to an outer end of one or more of the traces.

Abstract: A cell placement is generated for a microelectronic circuit chip. Interconnect points for cell nets are calculated, for example, as gravity points of the cells of the respective nets. Optimal positions for external connection terminals or pads along the border of the circuit are calculated as being the closest positions to the respective interconnect points. The total wirelength of the placement is calculated as including the distances between the interconnect points and the respective pads. Where initial location of the pads results in overlap thereof, clusters of pads are identified and expanded to remove the overlap. Concatenated overlapping clusters resulting from expansion are treated as new clusters and subsequently expanded until all overlap is eliminated. The centers of gravity of the clusters are preserved. During the overlap removal process, initial rectangular coordinates of the pad positions are converted into linear coordinates along the border.

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate.

Abstract: On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer.

Abstract: A data register for providing data values to an n-element parallel processing array includes a memory buffer having first and second memory modules, where each module includes n columns of data values. An address decoder receives an address for accessing n data values at a time from the memory modules and asserts address values to access corresponding rows of the first and second memory modules. Select logic selects between respective columns of the first and second memory modules to retrieve the desired data values according to a predetermined order. A shift network reorders the data values into the correct order, if necessary, and provides the retrieved data values to the processing array. The select logic and shift network preferably include arrays of multiplexers. In particular, the select logic preferably includes an array of n 2:1 multiplexers, and the shift network preferably comprises an array of n.times.n:1 multiplexers.

Abstract: Disclosed is a node loop port core for use in a Fibre Channel high speed data system for implementing transmission protocol and loop arbitration. The node loop core converts incoming data from 10 bit format to 8 bit format, checks frame CRC, parses frames, and steers the results to any one of a number of buffers. The buffers function as loading areas for incoming frames and are not part of NL core. In transmit operation, the node loop core chooses a loaded buffer to service, assembles frames, generates and adds CRC to frames, encodes the result from 8 bit to 10 bit format and then transfers the results. All control functions associated with primitive signals and sequences are handled by the node loop core. The core follows established Fibre Channel arbitration rules and recognizes all necessary primitive signals and primitive sequences for proper operation of the arbitrated loop.

Abstract: A method of choosing non-scan I/O nodes to replace with scan I/O nodes so as to allow the greatest amount of proprietary information to be removed from an ASIC core netlist which is to be supplied to an ASIC customer, includes the steps of assigning weights to core gates based upon how competitively sensitive those gates are determined to be, assigning a value to each non-scan I/O node based upon the sum of weights of all gates to which the I/O node is connected, and replacing the non-scan I/O node having the greatest value with a scan node. Gates that are within the timing shell are assigned a weight of zero. I/O nodes that are performance critical are assigned a value of zero, and the weights of all gates connected to such performance-critical I/O's are also set to zero. The I/O node selection process is iterative, with the weight of a gate being set to zero when it is connected to more non-scan I/O nodes than are remaining to be chosen.

Abstract: A thyristor device includes first and second terminals, a PNPN thyristor structure including first P-region, a first N-region, a second P-region and a second N-region disposed in series between the first and second terminals, and an electrode for inducing an electric field into the second P-region. The induced electric field increases the number of charge carriers in the second P-region, and enables the device to be triggered at a lower voltage applied between the first and second terminals. The electrode includes an insulated gate, and can be connected to either the first or second terminal. The gate can include a thick field oxide layer, or a thin oxide layer to further reduce the triggering voltage. A differentiator including a capacitor connected between the first terminal and the electrode and a resistor connected between the second terminal and the electrode prevents false triggering during normal operation.

Abstract: Composite bond pad structure and geometry increases bond pad density and reduces lift-off problems. Bond pad density is increased by laying out certain non-square bond pads which are shaped, sized and oriented such that each bond pad closely conforms to the shape of the contact footprint made therewith by a bond wire or lead frame lead and aligns to the approach angle of the conductive line to which it is connected. Alternating, interleaved, complementary wedge-shaped bond pads are discussed. Bond pad liftoff is reduced by providing an upper bond pad, a lower bond pad and an insulating component between the upper and lower bond pads. At least one opening is provided through the insulating component, extending from the bottom bond pad to the upper bond pad. The at least one opening is aligned with a peripheral region of the bottom bond pad and is filled with conductive material.

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement.

Abstract: Disclosed is a wafer clamp which holds a wafer in place during chemical vapor deposition processes. The wafer clamp includes (1) a clamp body having an inner facing portion and an outer facing portion; and (2) an overhang member attached to and extending inwardly from the inner facing portion of the clamp body. The clamp is designed such that when it holds the wafer, the overhang member extends over the wafer's peripheral region and is separated from that peripheral region by at least a predefined distance. The peripheral region is a region on the wafer's upper face that resides near the perimeter of the upper face. The predefined distance is chosen such that during deposition, a layer of material does not contact both the wafer face and the overhang member. The predefined distance is at least about 100 times the thickness of the layer of material.

Abstract: A lid is sealed to an integrated circuit package by a method that uses a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The pressure foot is retracted against the spring bias while secondary jig index pins are meshed with corresponding sockets in the fabrication boat that are aligned with the package position on the boat. When the pins and sockets are meshed, the pressure foot is released to apply optimal assembly force at the package center normal of the package lid plane.

Abstract: A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Abstract: According to the present invention, a process for use with automatic test equipment ("ATE") for determining a propagation delay in a semiconductor circuit is provided. In one embodiment of the invention, the process comprises the steps of determining an expected delay time by interpolating a first simulation capacitance, a second simulation capacitance, and an ATE capacitance, with a first simulated delay time and a second simulated delay time, the simulated delay times corresponding to the first and second simulated capacitances respectively, testing the semiconductor circuit with the ATE to determine an ATE delay time, and comparing the ATE delay time with the expected delay time to determine whether the propagation delay is acceptable.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery. First and second terminals are formed in the active area adjacent to two vertices of the triangle respectively, and first to third gates are formed between the first and second terminals. The gates have contacts formed outside the active area adjacent to a side of the triangle between the two vertices. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor are selected for each device to provide a desired AND, NAND, OR or NOR function. A third terminal can be formed between two of the gates and used as an output terminal to provide an AND/OR logic function. The devices are interconnected using three direction routing based on hexagonal geometry.