Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing.

Abstract: A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit's modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

Abstract: For physical protection and to reduce stress, an electronic device (10) is mounted within a cavity in a housing (14) which constitutes an encapsulating member. The housing is preferably formed as two premoulded piece parts (14a, 14b). A leadframe (12) extends into the housing (14) in the manner of a sandwich construction. The device (10) may be mounted on a heat sink (16).

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: Method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated. The large scale field further includes a custom portion and a standard portion of functional components. Reticle formation of the standard portion involves optical correction techniques. Reticle formation of the custom portion may involve standard reticle formation techniques.

Abstract: A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.

Abstract: A method of producing a placement of cells for a microelectronic integrated circuit in accordance with specified cell interconnects includes constructing a hierarchial cluster tree based on the interconnects in which a lowest level of the tree includes clusters of interconnected cells, and each successively higher level includes clusters of interconnected clusters from a successively lower level. Clusters in each level are merged by a min-cut operation. Clusters of each successively lower level are then placed within clusters of each successively higher level in progressively decreasing order of levels. Clusters are placed in each level by computing a current gravity point for each cluster in accordance with the cells therein, computing a new gravity point for each cluster in accordance with the current gravity points and the interconnects, and moving each cluster from the current gravity point to the new gravity point.

Abstract: An improved MOS-type integrated circuit structure, and a method of making same, are described wherein a diode is electrically connected between the polysilicon gate electrode and the semiconductor substrate, and physically located in the substrate below the contact area of the polysilicon gate electrode so that no extra lateral space is needed to provide such a diode connection between the polysilicon gate electrode and the substrate. The junction is formed in the substrate in a region where the contact area of the gate electrode is usually positioned over field oxide. An opening is provided for the diode in the field oxide region of the substrate, by masking off an additional portion of the substrate, when the field oxide is initially grown, to provide for location of the diode therein.

Abstract: A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

Abstract: A phase-locked loop includes a phase/frequency detector, a charge pump, a voltage-controlled oscillator and a frequency divider coupled together to form a feedback loop, the feedback loop having a filter node between the charge pump and the voltage-controlled oscillator for coupling to an off-chip loop filter. A first electrostatic discharge (ESD) protection device is coupled to the filter node, which has leakage path through which a leakage current flows. A filter leakage cancellation circuit is coupled to the filter node and includes a second ESD protection device which generates a reference current that is equal to the leakage current. The filter leakage cancellation circuit applies the reference current to the filter node such that the reference current is opposite to and cancels the leakage current.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a hexagon, and includes an active area formed within the periphery. A first terminal and a second terminal are formed in the active area adjacent to edges of the hexagon that are separated by another edge. First to third gates are formed between the first and second terminals, and have gate terminals formed outside the active area adjacent to other edges of the hexagon. The power supply connections to the first and second terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired AND, NAND, OR or NOR function. The devices are interconnected using three direction routing based on hexagonal geometry.

Abstract: A lead frame for a multiplicity of terminals, in particular of large-scale integrated semiconductor chips, arranged in a very confined space and consisting of metallic conductors which converge from large outer spacings toward the terminals and can be connected to the terminals. The lead frame allows a high number of terminals with a low degree of spacing of the conductors to be produced. The conductors are produced in the outer region by a conventional production method and at their ends pointing toward the terminals by laser cutting of a uniformly metallic material.

Abstract: An analog to digital converter has an analog signal input, reference voltage divider and a plurality of comparators. Each comparator has a first input connected to said analog signal input and a reference input connected to receive a respective predetermined reference voltage from the reference voltage divider. In addition, test mode circuitry is provided for feeding a sequence of test voltages from the voltage divider to the first input of the comparators in a test mode. A decoder is connected to an output of each comparator for generating a binary output signal representative of an input analog signal.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of microelectronic devices formed on the substrate. Each device has a periphery defined by a triangle, and includes an active area formed within the periphery, a central terminal formed in a central portion of the active area, and interconnected first to third terminals formed in the active area adjacent to vertices of the triangle respectively. First to third gates are formed between the first to third terminals respectively and the central terminal, and have contacts formed outside the active area adjacent to the sides of the triangle. The power supply connections to the central terminal and the first to third terminals, the conductivity type (NMOS or PMOS), and the addition of a pull-up or a pull-down resistor is selected for each device to provide a desired OR, NOR, AND or NAND function.

Abstract: A stackable heat sink assembly is formed by press-fit assembly of two or more identical fin layers. Each fin layer is formed using powdered metallurgy and has a button-like projection extending from its bottom surface and a recess opening in its top surface. The button-like projection and recess opening are sized and shaped such that an interference fit is formed when the button-like projection of one fin layer is pressed into the recess of another fin layer. The use of an adaptor to increase or decrease the effective size of the button-like projection of the bottommost fin layer is described. Relieving gases that may be entrapped in the recess during assembly is described. Circular, elliptical and polygonal shapes (outlines) for the fin layers are described.

Abstract: An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register.

Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

Abstract: A process monitor and a method of using the same to determine the relative strength of a semiconductor fabrication process are disclosed. An impedance control output from an impedance controller circuit located on a semiconductor device is retrieved. Based upon a value of the retrieved impedance control output, the relative strength of the semiconductor fabrication process used to fabricate the semiconductor device is determined.

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.