Abstract: A semiconductor cell layout definition is used to define a semiconductor cell during a layout process of an integrated circuits. The semiconductor cell performs a logical function which is implemented by one or more interconnected transistors. The cell layout definition includes a layout pattern of the interconnected transistors, a transistor width input variable, a cell loading input variable and geometry data for the interconnected transistors. The geometry data for at least one of the transistors is a function of the transistor width input variable. The cell layout definition further includes a propagation delay which is a function of the transistor width and the cell loading input variables. The transistor width input variable allows the widths of the transistors in the cell to be optimized during the layout process to reduce timing violations and minimize power consumption.

Abstract: Signal area efficiency in integrated circuit designs is improved by increasing the information efficiency of signal wiring on an integrated circuit. Candidate signals are selected for combination by prioritizing signals according to length of travel, travel path, and information content. Signals with low information content and with greater distance between endpoints make poor utilization of fixed wiring and provide the best candidates for improvement. Candidate signals which travel similar (substantially parallel) paths from point to point across the integrated circuit are combined to improve chip area utilization efficiency. A variety of techniques are described for combining low-information-content signals onto a small number of wires, transmitting them over the small number of wires, and re-expanding them at their destination. Assuming that the combining/expanding circuitry occupies less space than the point-to-point wiring which would otherwise be required, there is a net reduction in chip area.

Abstract: A method for manufacturing an ohmic contact on a semiconductor device, as disclosed herein, includes a first step of etching a via through a non-conductive layer formed over a partially fabricated version of the semiconductor device. This step exposes a region of a device element such as a source, gate electrode, etc. Next, an ohmic contact layer including tantalum and silicon is deposited over the partially fabricated device and in the vias by sputtering in an argon atmosphere. Thereafter, and in the same processing apparatus, a barrier layer including a tantalum silicon nitride is deposited over the ohmic contact layer. Then an aluminum alloy metallization layer is directly deposited on the partially fabricated device at a temperature of at least 650.degree. C. At this deposition temperature, the metallization layer conformally fills the via, thereby producing a stable, uniform contact.

Abstract: A chemical vapor deposition apparatus includes a gas manifold having a first gas flow port through which a gas flow path extends, and a first peripheral surface which extends about the first gas flow port. The chemical vapor deposition apparatus further includes a second gas flow port through which the gas flow path extends, and a second peripheral surface extending about the second gas flow port. A connection of the gas manifold is provided such that the first and second peripheral surfaces substantially mutually engage intended for providing a substantial seal of the gas flow path. A groove is provided in at least one of the first and second peripheral surfaces and extends so as to communicate with at least one of the first and second gas flow ports. The groove facilitates flow of a test gas therein from outside the chemical vapor deposition apparatus towards the respective gas flow port.

Abstract: A process and structure are disclosed for inhibiting the channeling of dopant through the polysilicon gate electrode into a semiconductor substrate during implantation of source and drain regions in the substrate during the formation of MOS devices. After deposition over a semiconductor substrate of a polysilicon layer which will be subsequently patterned to form a gate electrode, an amorphous layer of silicon is formed over the polysilicon layer. This amorphous silicon layer is then treated with a material such as a nitrogen-bearing material capable of inhibiting grain growth and recrystallization of the amorphous silicon during subsequent high temperature processing. The amorphous silicon and polysilicon layers are subsequently conventionally patterned to form the gate electrode. The structure is then implanted without channeling of the dopant ions through the gate electrode into the underlying portion of the substrate where the channel of the MOS device will be formed.

Abstract: An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance s.sub.min from the. The lines are constructed until they reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M.

Abstract: A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer.

Abstract: A multiple match detection circuit including an array of N and P-channel pull-up and pull-down devices receiving a corresponding array of hit line signals for developing complementary bit line signals, which are provided to the respective inputs of a differential amplifier. Respective buffers drive the bit line signals to a maximum voltage differential in normal mode. For each hit line asserted, the pull-up and pull-down devices modify the voltage of the corresponding bit line by an incremental amount, thereby decreasing the bit line differential. The differential amplifier switches to indicate an error when the polarity of the differential voltage between the bit lines is reversed relative to the normal state. Any given single hit line does not cause enough of a voltage change to reverse the polarity of the differential voltage of the bit lines.

Abstract: A planar substrate is attached to a face of a semiconductor die. The semiconductor die is electrically connected to a printed wiring board and encapsulation material covers the peripheral edges of the planar substrate, semiconductor die, and means for interconnecting the die and printed wiring board. An exterior face of the planar substrate remains exposed and may be utilized in pick and place automatic assembly. The exterior face of the planar substrate may also be utilized for attachment of an external heat sink for improved heat transfer from the semiconductor device. The planar substrate may be comprised of silicon, ceramic, metal or any other stiff material so long as the temperature coefficient of expansion is similar to that of the semiconductor die. A flip-chip semiconductor die may also be utilized without a planar substrate wherein the nonactive face of the die is exposed.

Abstract: A fast memory system including one or more asymmetrical sense amplifiers precharged to a first logic state and optimized to slew very fast towards the first logic state. Each sense amplifier is coupled to a corresponding pair of complementary bit lines, which are preferably precharged. When enabled, each sense amplifier tends towards an opposite, default logic state opposite the first logic state when sensing the precharged bit lines. Control logic enables a corresponding precharge amplifier to precharge the bit lines, and then enables the sense amplifier after the assertion of a clock signal. Also, the control logic enables a corresponding pull-up device to precharge the output of each sense amplifier. Thus, the sense amplifier begins in the first, precharged logic state and slews towards the opposite, default logic state. The control logic then asserts a word line select signal to a corresponding memory cell, which drives a voltage differential on the bit lines to assert a data bit.

Abstract: A semiconductor device assembly having external connections, including power supply connections such as to a power source or ground, is made without resort to bond fingers. Rather, external connections are directly made from a semiconductor die to a conductive layer. The conductive layer is disposed on one surface of a printed wring board and is divided into electrically insulated conductive segments. Each of the conductive segments is connected to an external connection, and includes one or more interconnects that can be directly connected to a semiconductor die. The conductive segments are surrounded by an array of bond fingers which serve to connect the semiconductor die to further external connections, such as signal connections. The present invention is especially advantageous in the fabrication of pin grid array (PGA) and ball grid array (BGA) type integrated circuit packages.

Abstract: A word line decoder gate including a plurality of parallel-coupled devices coupled to a common node for receiving and decoding an address upon assertion of a clock signal, where each parallel device receives a corresponding address signal or its inverted counterpart depending upon the particular address being decoded. A precharge device is coupled to the common node for keeping it at a first voltage level until the clock signal is asserted, and two series coupled charge devices are coupled between a source voltage and the common node, which charge devices attempt to charge the common node to a second voltage level during a time period while the clock signal is asserted and a delayed clock signal remains deasserted. A delay device receives the clock signal and asserts the delayed clock signal. However, any one or more of the parallel devices, if activated, provides a current path from said common node to override the two charge devices to keep the common node substantially at the first voltage level.

Abstract: A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing.

Abstract: A bias voltage generator for a voltage controlled oscillator is described. In one aspect of the invention, the bias voltage generator includes a biasing circuit to generate a minimum clock output at zero operating voltage, and includes a common mode rejection circuit for the BIASN and BIASP control voltages for the differential delay stages and a IDD test current shut-down circuit. A differential delay stage is described that includes a current source controlled by the BIASN and BIASP control voltages from the bias voltage generator, a resistance linearization circuit for current controlling transistors of a BIASN circuit, and a process variation circuit for compensating for temperature and process variations. The improved characteristics of the resulting VCO permits high frequency operation with a relatively low gain, relatively constant gain throughout operating voltage range, improved noise rejection capabilities, increased speed of delay stage, and reduced output signal swing.

Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

Abstract: A lid is sealed to an integrated circuit package using a spring biased pressure foot that is structurally carried by a secondary loading jig to impose sealant curing load on the lid. The secondary jig attaches to the fabrication boat at a position indexed to apply optimal assembly force at the package center normal of the package lid plane.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: An MOS structure is disclosed which is provided with a trench in the substrate adjacent the channel region of the substrate, i.e., adjacent the area of the substrate over which the gate oxide and gate electrode are formed. The region of the substrate beneath the trench is lightly doped to provide a deeper LDD region in the substrate between the channel and the drain region so that electrons traveling through the channel to the drain region follow a path deeper in the substrate and farther spaced from the gate oxide in the region of the substrate between the source region and the drain region where high fields are encountered by electrons traveling through the channel from the source region to the drain region.

Abstract: A flexible architecture for the Super Core for implementing the FC-1 transmission protocol and the FC-2 signalling (framing) protocol in a 1.0625 Gbit/second Fibre Channel, which realizes 80 Mbytes/second sustained throughput. The architecture supports multiple, concurrent, open, and active exchanges and sequences with the use of an embedded control processor with all necessary time-critical functions performed in hardware and less critical performed by the embedded processor firmware.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.