Patents Assigned to LSI Logic
  • Plasma etching process control
    Patent number: 5362356
    Abstract: A passive, in-line method of monitoring film removal (or deposition) during plasma etching (or deposition) based on interference phenomena is disclosed. Plasma emission intensity is monitored at a selected wavelength, without additional illuminating apparatus, and variations in plasma emission intensity are correlated to remaining film thickness, etch rate and uniformity, and etch selectivity. The method is useful in conjunction with nitride island etch, polysilicon etch, oxide spacer etch, contact etch, etc. The method is also useful in determining a particular remaining film thickness (e.g., just prior to clearing) at which point the etch recipe can be changed from a high-rate, low selectivity etch to a low-rate, high-selectivity etch.
    Type: Grant
    Filed: January 14, 1992
    Date of Patent: November 8, 1994
    Assignee: LSI Logic Corporation
    Inventor: Philippe Schoenborn
  • Method and system for fabricating IC packages from laminated boards and heat spreader
    Patent number: 5357672
    Abstract: A method and system for producing a plurality of integrated circuit packages having heat spreaders attached thereto. A planar metal sheet having predefined openings allows the addition of discrete bypass capacitors to the integrated circuit package. The planar metal sheet laminates to a plurality of laminated printed wiring boards. The metal sheet is then cut into sections resulting in individual packages. Each package has a cavity in which an integrated circuit die is placed therein. The integrated circuit die is in close thermal communication with the heat spreader of the package and connects to the conductive paths of the printed wiring boards. The invention is especially advantageous in manufacturing in quantity plastic pin grid array (PPGA) and plastic ball grid array (PBGA) integrated circuit packages.
    Type: Grant
    Filed: August 13, 1993
    Date of Patent: October 25, 1994
    Assignee: LSI Logic Corporation
    Inventor: Keith G. Newman
  • Method of making integrated circuit structure with programmable conductive electrode/interconnect material
    Patent number: 5358886
    Abstract: An integrated circuit structure, and a method of making same is disclosed wherein one or more patternable busses of conductive material (such as polysilicon) interconnect electrode strips (such as gate electrode strips) of the same conductive material formed over active areas (such as MOS islands). The busses are formed on the structure over field oxide portions thereon during the initial step of patterning the layer of conductive material to expose the active areas and to form the electrodes thereover. After further processing to form other electrode regions in the active areas (e.g., source and drain regions in N-MOS and P-MOS islands), but prior to formation of an insulation layer over the structure for formation of a metal layer thereon, the busses are subjected to a further patterning step to form custom interconnections, as desired, between various electrodes in the integrated circuit structure.
    Type: Grant
    Filed: July 1, 1993
    Date of Patent: October 25, 1994
    Assignee: LSI Logic Corporation
    Inventors: Abraham Yee, Stanley Yeh, Tim Carmichael, Gobi Padmanabhan
  • Ceramic spacer assembly for ASM PECVD boat
    Patent number: 5356475
    Abstract: A method and apparatus for eliminating radio frequency arcing in a wafer coating plasma process, called PECVD, is disclosed. In the PECVD process, semiconductor wafers are mounted on graphite paddles of a boat assembly held inside a furnace tube. The graphite paddles are arranged in parallel planes and held in a spaced apart relationship by ceramic rods. The present invention spacers have small diameter end portions and are disposed coaxially on the ceramic rods. The spacers support the graphite paddles only on the small diameter end portions, thus separating the graphite paddles from the ceramic rods, as well as simultaneously maintaining the spacing between adjacent graphite paddles on a common ceramic rod. An optional end spacer is disposed on the end of the ceramic rod and is held in place by an optional ceramic nut screwed onto threads formed on the end of the ceramic rod.
    Type: Grant
    Filed: February 22, 1993
    Date of Patent: October 18, 1994
    Assignee: LSI Logic Corporation
    Inventors: Salvatore Diiorio, Quentin Jackson
  • Formation of uniform dimension conductive lines on a semiconductor wafer
    Patent number: 5354706
    Abstract: A method for forming uniformly sized features, such as polysilicon lines or gates, or such as conductive lines, on a semi conductor wafer having a planar upper surface is described which minimizes variations in the critical dimensions of the features. The technique allows a substantially uniform overlying layer, such as photoresist, to be formed above the layer intended to contain the features. The method can be applied to forming isolation trenches around active areas on the semiconductor wafer, overfilling the trenches with an insulating material (e.g., oxide), polishing back the oxide to a planar surface, depositing a planar layer of a conductive material (e.g., poly), and depositing a planar layer of a photoresist. The planar layer of photoresist, being deposited over a planar layer of conductive material has substantially uniform thickness and correspondingly uniform reflectivity.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: October 11, 1994
    Assignee: LSI Logic Corporation
    Inventor: Roger Patrick
  • High power dissipating packages with matched heatspreader heatsink assemblies
    Patent number: 5353193
    Abstract: A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: October 4, 1994
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Manian Alagaratnam, Qwai H. Low, Seng-Sooi Lim
  • Process for dynamic control of the concentration of one or more reactants in a plasma-enhanced process for formation of integrated circuit structures
    Patent number: 5348614
    Abstract: A process for dynamically adjusting the concentration of one or more reactants in a plasma assisted process, such as a plasma etch process or a plasma deposition process, is described. The concentration of one or more reactants, as well as the concentration of a non-reactive gas, in a plasma enhanced process for the formation of an integrated circuit structure is quantitatively monitored by actinometry to derive a ratio of such concentrations of reactant to non-reactant. The concentration of the reactant or reactants in the plasma processing chamber is then maintained in the chamber by adjusting the flow of such reactant or reactants into the chamber based on changes in such ratio based on such continuous quantitative monitoring of the both the concentration of the reactant or reactants and that of the non-reactive (non-changing concentration) component.
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: September 20, 1994
    Assignee: LSI Logic Corporation
    Inventor: Chris Jerbic
  • Preformed planar structures employing embedded conductors
    Patent number: 5347162
    Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of reflow solder joints between conductive bumps on the die and corresponding conductive bumps of the substrate. In one embodiment, conductive elements embedded in the preformed planar structures extend at least partially into the through holes, forming electrical connections with the corresponding solder joints. The conductive elements can be used to electrically connect one solder joint to another within the interposer, and/or may extend beyond an edge of the interposer to provide for electrical probing of or connection to the solder joints. In one embodiment, the conductive elements are extended outside of the preformed planar structure to form "pins" or leads of the flip-chip structure.
    Type: Grant
    Filed: August 12, 1993
    Date of Patent: September 13, 1994
    Assignee: LSI Logic Corporation
    Inventor: Nicholas F. Pasch
  • Identifying and compensating for slip-plane dislocations in photolithographic mask alignment
    Patent number: 5345310
    Abstract: Techniques for identifying and determining the orientation, magnitude, and direction of slip plane dislocations transecting semiconductor dies are described, whereby a four point alignment pattern is examined for "squareness" and size integrity. Lack of squareness or significant change in apparent size of various aspects of the alignment pattern indicate slip-plane dislocations. The magnitude, orientation and direction of the dislocations are determined geometrically from measurement of the alignment pattern. Various other aspects of the invention are directed to optimal alignment of a photolithographic mask to a die which has experienced a slip-plane dislocation, and to discrimination between slip-plane dislocation and die-site rotation.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: September 6, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Nicholas F. Pasch, Joe Zelayeta
  • Method of increasing the layout efficiency of dies on a wafer and increasing the ratio of I/O area to active area per die
    Patent number: 5340772
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Techniques for providing high I/O count connections to semiconductor dies
    Patent number: 5340771
    Abstract: Techniques for providing semiconductor packages capable of forming connections to "high I/O" semiconductor dies is described, wherein there are at least two distinct pluralities of conductive lines. Leadframe-type packages and substrate-based package embodiments are described.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rostoker
  • Adjustable height work holder for bonding semiconductor dies
    Patent number: 5340011
    Abstract: In a semiconductor wire bonder, the need for frequently changing chucks and re-focusing optical equipment for each different die/package thickness combination is alleviated by providing an adjustable stop mechanism lifting the upward displacement of the die/package off of a carrier. The adjustable stop mechanism includes a first, stationary bracket having a leg extending towards a movable lifting member of the bonder, and a second bracket mounted to the movable lifting member. A set screw extending through the leg of the first bracket limits the upward movement of the movable member, and ensures that the front surface of a die being bonded is at an optimum position for bonding.
    Type: Grant
    Filed: December 9, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Antonio Sanchez
  • Image-sensing display panels with LCD display panel and photosensitive element array
    Patent number: 5340978
    Abstract: A camera comprising various arrangements for employing optical elements in association with photosensitive elements are described. In some of the arrangements, the optical elements are formed integrally with a substrate containing the photosensitive elements. In other arrangements, an optical element is mounted to a package, or the like, containing the substrate and photosensitive elements. In other arrangements, two or more optical elements are employed, including conventional refractive elements, refractive focusing elements, and refractive beam splitting elements. Utility as solid state image sensors is discussed. Utility for monochromatic and color imaging is discussed. Various devices based on such camera arrangements and methods of making same are discussed.
    Type: Grant
    Filed: April 21, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, David E. Sanders
  • Method of increasing the layout efficiency of dies on a wafer, and increasing the ratio of I/O area to active area per die
    Patent number: 5341024
    Abstract: Certain non-square dies, such as triangular dies, greatly elongated rectangular dies, parallelogram dies, trapezoidal, and the like, are able to be laid out in the area of a circular semiconductor wafer more "efficiently" than square dies. Further, a peripheral area of these certain non-square dies is advantageously increased relative to the area contained within the peripheral area, to accommodate increased I/O connections to the active elements of the die.
    Type: Grant
    Filed: November 18, 1992
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Michael D. Rosotker
  • Equipment alignment docking system
    Patent number: 5339940
    Abstract: A piece of movable equipment is provided with a male docking bar (10) . An immovable piece of equipment is mounted to an immovable fixture which has a female docking bar (28). The female docking bar (28) has freedom to move in a first axis. The movable piece of equipment is brought into contact along a second, orthogonal axis to meet the immovable piece of equipment, at which point lugs (12) on the male docking bar mate with corresponding holes (30) on the female docking bar. The male locking bar can then be interlocked (16, 32) to the female docking bar. The movable piece of equipment can then further be moved along the first axis.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: August 23, 1994
    Assignee: LSI Logic Corporation
    Inventor: Alan Simms
  • Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC
    Patent number: 5339262
    Abstract: A technique for testing the performance of a target electronic system ultimately employing an ASIC comprising a core cell and surrounding logic, using an inchoate (designed, but not yet fabricated) ASIC on an interim basis. In one embodiment, a Q-part, or qualification part, which is essentially a bond-out of the core cell, is used in conjunction with programmable logic devices configured to perform the function of the surrounding logic. The Q-part and programmable logic are interconnected on a pod, and plugged into an interim version of a target electronic system. In another embodiment, the Q-part is software-simulated and interconnected on the pod to programmable logic devices. The programmable logic devices may be programmed either on-pod or off-pod, and signals incident to the operation of the pod plugged into the interim electronic system can be monitored and controlled.
    Type: Grant
    Filed: July 10, 1992
    Date of Patent: August 16, 1994
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, David Gluss, Tom Harrington
  • Packaging of electronic devices
    Patent number: 5338899
    Abstract: An electronic device (10) encased within a moulded package body (11) has a leadframe (12) extending therefrom. In order to protect the leads (16) for the electronic device a guard ring (14) is provided on the leadframe. By making the guard ring independently of the moulded package body and fitting it separately to the leadframe one can deal with packages of any size in a simple manner and irrespective of the material of the package body (11).
    Type: Grant
    Filed: May 14, 1992
    Date of Patent: August 16, 1994
    Assignee: LSI Logic Corporation
    Inventor: Trevor C. Gainey
  • Fixture for testing mounting integrity of heat sinks on semiconductor packages, and method of testing
    Patent number: 5337614
    Abstract: A reliable, repeatable, well-characterized, safe technique for testing the mounting integrity of heat sinks adhered to semiconductor packages is disclosed. Generally, a semiconductor package is secured in a tensiometer, the heat sink is clamped and secured to the spindle of the tensiometer, and a stud-pull type test is conducted.
    Type: Grant
    Filed: August 20, 1992
    Date of Patent: August 16, 1994
    Assignee: LSI Logic Corporation
    Inventors: Xin H. Jiang, Scott Kirkman
  • Techniques for uniformizing photoresist thickness and critical dimension of underlying features
    Patent number: 5330883
    Abstract: Changing (varying, irregular) resist thickness on semiconductor wafers having irregular top surface topography or having different island sizes, affects the percent reflectance (and absorption efficiency) of incident photolithographic light, and consequently the critical dimensions of underlying features being formed (e.g., polysilicon gates). A low solvent content resist solution that can be applied as an aerosol provides a more uniform thickness resist film, eliminating or diminishing photoresist thickness variations. A top antireflective coating (TAR) also aids in uniformizing reflectance, despite resist thickness variations. The two techniques can be used alone, or together. Hence, better control over underlying gate size can be effected, without differential biasing.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: July 19, 1994
    Assignee: LSI Logic Corporation
    Inventor: Mario Garza
  • Integrated circuit test reticle and alignment mark optimization method
    Patent number: 5329334
    Abstract: A test reticle and alignment mark optimization method is provided for determining the optimal alignment mark size for the efficient and accurate alignment of process layers during integrated circuit manufacture. The test reticle includes a number of orthogonally arranged alignment marks of various types and sizes and one or more registration structures. The method involves the steps of determining an initial expected range of alignment mark sizes on the test reticle which are suitable for a particular application; applying the test reticle pattern to test wafers; further processing the test wafers; measuring the alignment signals produced by scanning the alignment marks in the initial expected range; quantifying the alignment signal quality; and fitting the quantified alignment signal quality to a statistical model to determine a range of optimal alignment signal dimensions.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: July 12, 1994
    Assignee: LSI Logic Corporation
    Inventors: Randy Yim, Christopher Neville