Abstract: A method of producing an antifuse includes introducing nitrogen by ion implantation means into the substrate. An oxide dielectric layer is then formed on the nitrided substrate in a wet oxidation ambient. The conditions of the ion implantation and the oxidation are controlled to generate a dielectric with uniform thickness and a low breakdown voltage when subjected to a high electric field.

Abstract: A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a test analyzer, generating a second predetermined data pattern within the test analyzer, and simultaneously transmitting the second test pattern to the device where the second test pattern is verified. The first and second test patterns may be the same or different, depending on the application. Further, the transmit and receive paths may be tested separately and independently in addition to simultaneously.

Abstract: A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.

Abstract: A system and method for deploying various versions of a BIOS system having configurable text strings. When a text string is required, the BIOS or configuration tool may retrieve a text string from the text string location. The executable BIOS and configuration tool may be common for many applications while the text strings may be changed for various applications. The text strings may be customized for various languages or applications without requiring recompiling the BIOS or configuration tool executable code.

Abstract: According to one embodiment, a method of testing an integrated circuit is provided. The quiescent current measuring of an integrated circuit is measured at two voltages. The functional relationship between the current measurements is determined and compared against a predetermined functional relationship to determine whether a defect exists in the integrated circuit.

Abstract: A bonding pad for an integrated circuit, where the bonding pad overlies a fragile dielectric layer. A lower metal layer stack overlies the fragile dielectric layer, and a hard dielectric layer overlies the lower metal layer stack. An upper metal layer stack overlies the hard dielectric layer, where the upper metal layer stack forms voids extending into the upper metal layer stack from an exposed upper surface of the upper metal layer stack. The voids define deformable protrusions in the upper surface of the upper metal layer stack, for at least partially absorbing forces applied to the bonding pad during a bonding operation. Electrically conductive vias extend from the lower metal layer stack through the hard dielectric layer to the upper metal layer stack, and electrically connect the lower metal layer stack to the upper metal layer stack.

Abstract: A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.

Abstract: A memory module is provided as well as a method for forming a memory module. The memory module includes a printed circuit board having opposed first and second outside surfaces. At least one via can extend through the printed circuit board and couples a conductor on one outside surface to a conductor on another outside surface. A semiconductor memory device on one of those outside surfaces can thereby be connected to one end of the via, with another semiconductor memory device on the opposing outside surface connected to the other end of the via. Preferably, the pair of memory devices are placed on a portion of each respective outside surface so that they essentially align in mirrored fashion with each other. Accordingly, any vias which extend from the footprint of one memory device will take the shortest path to the footprint of the other memory device, with the stubs between the footprint and the via being of essentially the same length and relatively short.

Abstract: A method and system for automatically guiding a user through a design flow for an integrated circuit are disclosed. The method and system include displaying a design flow user interface on a user's computer, where the user interface includes symbols corresponding to design flow process steps. The design flow process steps are defined with a set of rules, and user input for each step is analyzed for compliance with the rules. The user is allowed to proceed to a next step in the flow once it is determined that the previous steps have been completed successfully.

Abstract: A method and apparatus for probing semiconductor circuits using a wafer-mounted micro-probing platform. A platform or platen is affixed to the surface of a wafer. Probe manipulators are mounted on the platen, and probes extend from or are otherwise associated with the probe manipulators. The probe manipulators may be fixed in position, or they may be motorized to allow adjustment of the probe positions while in-situ. During probing, electrical signals are preferably sent to the probes viz.-a-viz. feedthrough interfaces. The platen which is affixed to the surface of the wafer effectively serves two purposes: 1) as a mounting point for the probe manipulators; and 2) to mechanically stiffen the wafer so that the wafer does not flex, thereby requiring re-positioning of the probes.

Abstract: A method of designing a packaged circuit, including a substrate and a circuit. The circuit is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known function and a known contact pattern. The circuit is designed by selecting desired functional blocks according to functions desired for the circuit. The substrate is designed with a plurality of standardized functional blocks. Each of the functional blocks has a known contact pattern, a known signal trace routing layer pattern, a known ground plane layer pattern, and a known power plane layer pattern. A given one of the substrate functional blocks is associated with a given one of the circuit functional blocks. The substrate is designed by selecting substrate functional blocks associated with the desired ones of the circuit functional blocks.

Abstract: A refetch logic propagates data from a first source to a link controller by default. The link controller prefetches data from the refetch logic to generate a first packet prior to receiving control of the transmission medium on which the data is to be transmitted. The refetch logic changes sources and propagates to the link controller data from a second source if necessary. At the same time, the refetch logic also causes the link controller to discard the first packet and generate a second packet from data provided by the second source.

Abstract: The present invention provides an integrated circuit (IC). In one embodiment, the IC includes a substrate and a plurality of gate array blocks located on the substrate. Each of the blocks includes a programmable gate array (PGA) containing at least a portion of a circuit design in an interconnect layer thereof, and a field-programmable gate array (FPGA) coupled to the PGA and capable of containing a configuration that augments the portion of the circuit design. In this embodiment, the PGA and the FPGA cooperate to effect the circuit design. In another aspect, the present invention provides a method of designing an IC. In yet another aspect, the present invention provides a method of manufacturing ICs.

Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.

Abstract: A storage controller is provided that allows data mirroring with hotspare where all drives take part in data storage. For each stripe written, a drive is designated as the hotspare. The hotspare is not a dedicated drive. Rather, the hotspare rotates as stripes are written to the drives. Thus, every drive is involved in data storage and load may be balanced among more drives. Furthermore, since each drive takes part in data storage, reconstruction after a drive failure takes less time.

Abstract: Structures and methods for non-intrusive testing of communication signals exchanged between two circuit boards via an intermediate interconnect board. In one aspect hereof, the functional signal normally exchanged between the circuits is latched during the exchange of test signals and the latched functional signal is utilized within the circuit that normally receives the functional signal to continue normal operations. In another aspect hereof, the test signals are exchanged over a dedicated test signal path between the two circuits. In another aspect hereof, the test signals are exchanged over the functional signal paths as out of band signals.

Abstract: A package for reducing signal cross talk between wire bonds of semiconductor packages. The package includes a semiconductor die having a plurality of bond pads formed thereon. The bond pads arranged in a first subset of bond pads and a second subset of bond pads. The package also includes a substrate having a plurality of contact points, the plurality of contact points are arranged in a first subset of contact points and a second subset of contact points. To reduce signal cross talk, the wire bonds are arranged such that a first subset of wire bonds are electrically coupled between the first subset of bond pads and the first subset of the contact points. The first subset of wire bonds have ball bonds formed on the first subset of bond pads and stitch bonds formed on the first subset of contact points respectively. A second subset of wire bonds are electrically coupled between the second subset of bond pads and the second subset of the contact points.

Abstract: A line interface couples a data transceiver to a transmission line via a transformer, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range. The line interface includes an input port for receiving an input signal voltage from an analog front end (AFE) chip, an output port, a line driver for amplifying the input signal voltage and supplying a transmit signal to the output port, a line port for sending the transmit signal and receiving a receive signal, termination resistors coupled between the output port and the line port, a receive signal port for supplying the receive signal to the AFE chip, a receive amplifier formed on the AFE chip coupled to the receive signal port, and a bridge network resistively coupling the line port and the output port to the receive signal port, the bridge network having a low-pass filter characteristic.

Abstract: Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f?N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N? inputs, where N? is 3n or 2*3n, and the N??N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N?1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.

Abstract: The present invention is a low complexity method for reducing the number of motion vectors required for bi-predictive frames or fields in digital video streams. The present invention utilizes the motion vectors located in the corner blocks of a co-located macroblock, rather than all motion vectors, when determining the motion vectors of a current block. This results in reduced resources in the computation of direct motion vectors for a bi-predictive frame or field.