Abstract: A method for analyzing electromigration and voltage drop effects in wire segments forming a power-bus grid of an integrated circuit. A floor plan design is created by mapping wire segments to various metal layers in the IC core. Digital, analog, and memory power zones indicating the power consumption of regions within the core are also mapped to the core. An equivalent circuit of the floor plan is generated in a netlist. The netlist is simulated, with the current density and voltage drop of power-bus wire segments calculated. Calculated current density and voltage drop values are analyzed in the floor plan design using a color map to indicate the current density and voltage drop levels of the wire segments. The designer can modify the floor plan design quickly and easily if the calculated current density and voltage drop values indicate potential electromigration or voltage drop problems.

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to generate an output signal and a clock signal in response to the plurality of samples and the plurality of phases. The clock signal is generally aligned with the output signal.

Abstract: A coaxial shield for a semiconductor chip includes: a top vertical shield wire formed in a top metal layer of a semiconductor chip wherein the top vertical shield wire has a selected length for providing a coaxial shield; a first side shield wire formed in an intermediate metal layer of the semiconductor chip; a first upper via formed in a first dielectric layer of the semiconductor chip that extends lengthwise parallel to the first side shield wire to electrically connect the first side shield wire to the top vertical shield wire along the selected length; a second side shield wire formed in the intermediate metal layer of the semiconductor chip having a length corresponding to the selected length wherein the second side shield wire extends lengthwise parallel to the first side shield wire; and a second upper via formed in the first dielectric layer that extends lengthwise parallel to the second side shield wire to electrically connect the second side shield wire to the top vertical shield wire along the len

Abstract: A delay line calibration circuit and method are provided in which a programmable master delay line drives a delay clock and has a propagation delay that is a function of a delay setting. A delay counter is clocked by the delay clock and has a delay count. A reference counter is clocked by a reference clock and has a reference count. A control circuit controls the delay and reference counters, compares a representation of the delay count to a representation of the reference count and responsively generates a modified value for the delay setting to reduce a difference between the representations of delay count and the reference count.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: The present invention is directed to a detector for a high-density magnetic recording channel and other partial response channels. The present invention presents a method for decoding a high rate product code and a decoder which uses this method, comprising receiving a high rate product code; using a row detector to find a most likely codeword and a most likely error sequence for each row; and using a column processor to correct any remaining errors based on column parity bits and the most likely error sequence of each row. In a first aspect of the present invention, the row detector is implemented through a 2-VA detector. In a second aspect of the present invention, the row detector is implemented through a conventional VA detector and a hank of matched filters.

Abstract: A method of analyzing substrate yield, where a substrate yield map and a substrate contact map are selected and overlaid to produce a composite map. First elements of the substrate yield map are compared to second elements of the substrate contact map to determine a degree of correlation between the first elements and the second elements. Additional substrate contact maps are repeatedly selected and the first elements of the substrate yield map are compared to the second elements of the additional substrate contact maps, and a degree of correlation between the first elements and each of the second elements for the additional substrate contact maps is determined and reported. The composite map having a highest degree of correlation between the first elements and the second elements is presented, and all composite maps that have at least a desired degree of correlation between the first elements and the second elements are presented.

Abstract: A wafer edge inspection method and apparatus include a review tool that captures images of the semiconductor wafer. According to various embodiments, the present invention also includes a map of points of interest proximate to the edge of the wafer, automatic image capturing at the points of interest, fake defect locations defining the points of interest, a database in which the images are stored and computer-searchable for detailed defect analysis, a software tool for controlling the method and apparatus and/or context information identifying the points of interest, the inspected wafer and/or the fabrication station/step preceding the inspection.

Abstract: Structure and methods for preserving lock requests by master devices on multiple buses each coupled to a port of a multiported device. The invention provides for arbitration among multiple ports of a multiported device to preserve the intent of a lock request to retain exclusive control of the bus over an extended period involving multiple bus transactions directed through a corresponding port. In a first exemplary preferred embodiment, an AMBA AHB compliant bus bridge or multiported slave device is coupled through its ports to multiple AHB buses each having one or more master devices coupled thereto. Logic circuits and methods associated with port arbitration for the bus bridge device or multiported slave device preserve the intent of HLOCK requests asserted by master devices on one of the AHB buses coupled to a port to preserve the intent of the lock request through port arbitration within the multiported device.

Abstract: For use in a wide-issue pipelined processor, a mechanism and method for reducing pipeline stalls between nested calls and supporting early prefetching of instructions in nested subroutines and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a program counter (PC) generator that generates return PC values for call instructions in a pipeline of the processor and (2) return PC storage, coupled to the PC generator and located in an execution core of said processor, that stores the return PC values and makes ones of the return PC values available to a PC of the processor upon execution of corresponding return instructions.

Abstract: Methods and associated structure for migrating storage devices between storage subsystems. A storage device to be removed from a storage subsystem is first “exported” by altering configuration data stored on the storage device. The altered configuration information helps assure that the storage device will be recognized as a foreign device in any storage subsystem into which it is subsequently inserted. Forcing recognition of the storage device as a foreign storage device in any subsystem helps assure predictability of the process of importing the storage device into a new system and helps reduce the risk of data loss when reinserting the storage device into a storage subsystem. Storage devices so migrated may include individual disk drives as well as entire volumes comprising one or more disk drives.

Abstract: An apparatus comprising a decode frame store, a B frame store, a first anchor frame store, and a second anchor frame store. The decode frame store may be configured to decode one or more free frames and generate one or more B video images and one or more anchor video images. The B frame store may be configured to receive the one or more B video images from the decode frame store. The first anchor frame store may be configured to receive the one or more anchor video images from the decode frame store. The second anchor frame store may be configured to receive the one or more anchor video images from the first anchor frame store.

Abstract: A prescaler generally comprising a first circuit, a multiplexer, and a second circuit. The first circuit may be configured to present a plurality of control signals in response to a first clock signal having a first frequency. The multiplexer may be configured to multiplex a plurality of data signals in response to the control signals to present a second clock signal having a second frequency that is a non-integer fraction of the first frequency. The second circuit may be configured to present the data signals in response to the second clock signal.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of a Serial ATA interface including a NCQ Serial ATA device is automatically detected. In this step, it is determined, preferably based on a value of the FPDMA (First Party Direct Memory Access) bit in a Task File Ram of the Serial ATA interface, whether the NCQ Serial ATA device is in a FPDMA Data Phase. When the NCQ Serial ATA device is in a FPDMA Data Phase, the Serial ATA interface is active (i.e., not idle). When Serial ATA is in an idle condition, idle time of Serial ATA interface is measured using a power down counter whose frequency is determined by a programmable register based on an input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state.

Abstract: An apparatus including a first processing circuit and a second precessing circuit. The first processing circuit may be configured to generate a plurality of reconstructed samples in response to one or more macroblocks of an input signal. The second processing circuit may be configured to determine availability of intra 4×4 prediction modes for each luma sub-block of a current macroblock in response to available reconstructed samples adjacent to the current macroblock.

Abstract: A method synchronizes serial data stream output from a multiple-port system. The multiple-port system includes a plurality of port devices. The method includes (a) timing a serial data stream at each port device, the serial data stream including a series of data frames, (b) generating a framing signal at each port device, the framing signal indicating a boundary of the data frame in the serial data stream, (c) supplying the framing signal to a next port device, and (d) synchronizing, at each next port, the timing of the serial data stream in response to the supplied framing signal.

Abstract: An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

Abstract: A semiconductor package for reducing signal cross talk between wire bonds of semiconductor packages by using a tier of input-output power bond pads between two tiers of signal bond pads. The package includes a substrate having a first surface and a second surface and a die attach area on the first surface of the substrate. A first tier of signal contacts is arranged around the periphery of the die attach on the first surface of the substrate. A second tier of signal contacts is arranged around the periphery of the die attach area on the first surface of the substrate. A power contact tier is also arranged around the periphery of the die attach area on the first surface of the substrate. The power contact tier is arranged between the first tier of signal contacts and the second tier of signal contacts to reduce signal noise and cross talk between the signal bond wires of the first tier and the second tier.

Abstract: Techniques for utilizing a bonding agent that allows a solder reflow process to occur at a lower reflow temperature. One area of use includes semiconductor device manufacturing processes. The bonding agent is placed between a solder ball and a contact surface. The bonding agent has a melting temperature that is lower than that of the solder ball. Reflow is then performed at a relative low temperature that is high enough for reflowing the bonding agent, yet at the same time, lower than what would be necessary to reflow the solder material. Since, the electrical system is not subjected to the high temperatures necessary for reflowing the solder material, the electronic system experiences less high-temperature related damage.

Abstract: A system identifies one or more devices having faults in a communication loop. The system includes an interface, a decision module, and a connection processor. The interface is configured for sending requests for information to each device of the communication loop and for receiving responses to the requests. The devices may include computer disk drives for use in a storage system. The requests may include Read-Link Status (RLS) commands sent to the computer disk drives. The RLS commands may provide diagnostics of the disk drives connected to the loop. The decision module is communicatively connected to the interface for weighting the responses of each device to identify the devices having the faults. The responses may be weighted based on the relative potential for disrupting operability of the system. The communication loop may include an FC loop that allows communications between a host system and the computer disk drives.