Abstract: A hardware assisted searching mechanism is provided that offloads the processor from searching operations. In a preferred embodiment, the hardware assisted searching mechanism performs a binary search of an associated 32 bit register against a binary search table that is set up by the firmware of the storage system. From this binary search table, an index into other structures stored in firmware is obtained that may be used to identify a target device. For example, when a search is to be performed due to receipt of an I/O operation, the firmware, i.e. software instructions stored in the persistent memory chip that are executed by the system processor, writes a 32 bit value to a hardware register that is used by the hardware assisted searching mechanism of the present invention. The hardware assisted searching mechanism performs a binary search of a binary search table based on the contents of the hardware register and returns an index of the entry in another hardware register.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

Abstract: The present invention relates to a method of fabricating planar semiconductor wafers. The method comprises forming a dielectric layer on a semiconductor wafer surface, the semiconductor wafer surface having vias, trenches and planar regions. A barrier and seed metal layer is then formed on the dielectric layer. The wafer is next place in a plating bath that includes an accelerator, which tends to collect in the vias and trenches to accelerate the rate of plating in these areas relative to the planar regions of the wafer. After the gapfill point is reached, the plating is stopped by removing the plating bias on wafer. An equilibrium period is then introduced into the process, allowing higher concentrations of accelerator additives and other components of the bath)] above the via and trench regions to equilibrate in the plating bath. The bulk plating on the wafer is resumed after equilibration.

Abstract: The present invention is a method and system for associating metadata with user data in a storage array in a manner that provides independence between metadata management and a storage controller's cache block size. Metadata may be associated with user data according to multiple fashions in order to provide a desired performance benefit. In one example, the metadata may be associated according to a segment basis to maximize random I/O performance and may be associated according to a stripe basis to maximize sequential I/O performance.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

Abstract: A circuit comprising a register stack and a control circuit. The register stack may be configured as (i) a plurality of segments addressable through a segment address signal and (ii) a plurality of registers within each of the plurality of segments. The plurality of registers are generally addressable through a register address signal. The control circuit may be configured to (i) store a plurality of register states, (ii) store a segment count signal, and (iii) present the segment address signal responsive to the plurality of register states, the segment count signal, and the register address signal.

Abstract: A method and apparatus are provided for interfacing between a data source and a tightly-coupled memory. In the method and apparatus, a write data word and a write address are received from the data source and latched in a first clock cycle within a write buffer along a write data path, between the data source and the memory. The write data word is encoded according to an error detection code along the write data path. The write address and the write data word are applied to the memory from the write buffer. The write data word is accessible to the data source from the write data path or the memory beginning with a second clock cycle, which is a next subsequent clock cycle to the first clock cycle.

Abstract: An integrated circuit is provided, which includes a transistor device under test, an AC drive circuit, an AC bias circuit and a DC bias circuit. The AC drive circuit generates an AC drive signal. The AC bias circuit biases the transistor device under AC bias conditions in response to the AC drive signal. The DC bias circuit biases the transistor device under DC bias conditions. A switch circuit selectively couples the transistor device to the AC bias circuit in an AC stress mode and to the DC bias circuit in a DC measurement mode.

Abstract: A device for use in a digital video receiver. The device generally comprising a demodulator circuit, a decoder circuit, a plurality of bi-directional buffers, and a circuit. The demodulator circuit may be configured to generate (i) a first clock signal compliant with a standard interface for the digital video receiver and (ii) a first plurality of data signals compliant with the standard interface. The decoder circuit may be configured to receive a second plurality of data signals compliant with the standard interface. The plurality of first bi-directional buffers may be configured to multiplex the first data signals with the second data signals at a plurality of data interfaces in response to the first clock signal. The circuit may be configured to generate a direction signal at a direction interface in response to the first clock signal to indicate a direction of the data interfaces.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of signals in response to one or more of a context index and a binary symbol. The second circuit may be configured to generate a series of output bits in response to the plurality of signals. The memory may be configured to transfer the plurality of signals between the first circuit and the second circuit.

Abstract: A data stream is transferred through a parallel data bus while the read or write strobe is adjusted. The resultant data is compared to the original data to detect errors with each data line of the parallel bus. The results are displayed on a grid whereby the characteristics of each line of the data bus may be visually understood. The characteristic image of the performance of the data bus may be used for debugging the bus, as well as for other uses wherein the performance is very highly characterized.

Abstract: An input/output characterization register is provided for characterizing an integrated circuit input or output. The register includes a normal data input, a characterization data input, and a data latch having a latch control input, a latch data input and a latch data output. The normal data input and the characterization data input are multiplexed with the latch data output to the latch data input.

Abstract: A method for transforming a customer's memory design into an RRAM memory design. A port mapping table is created that lists the ports of the customer memories, and an instance types table is created that lists the customer memories. For each customer memory that is listed in the instance types table, any virtual buffer nets are removed, and any virtual buffers are removed. Any loose nets so created are reconnected to an RRAM cell in the RRAM memory design. The customer memory instance are then removed. A constraints file is updated from customer memory port designations to RRAM port designations. Automated test logic is inserted into the RRAM memory design, layout on the RRAM memory design is performed, and timing constraints on the RRAM memory design are satisfied. A modified version of the RRAM memory design is returned to the customer for verification. The modified version is made using the port mapping table.

Abstract: The present invention is directed to a method and apparatus of automatic power management control for Serial ATA interface. In an exemplary aspect of the present invention, an idle or active condition of Serial ATA interface is automatically detected. When Serial ATA is in an idle condition, idle time of Serial ATA interface is counted using a power down counter whose frequency is determined by a programmable register based on input clock. When a power down counter value is equal to a first value, a request for a Partial power state is asserted, and Serial ATA interface is put into a Partial power state. When a power down counter value is equal to a second value, a request for a Slumber power state is asserted, and Serial ATA interface is put into a Slumber power state.

Abstract: A method for notification of a first new cell is disclosed. The method generally includes the steps of (A) generating a first report for a circuit design comprising a plurality of first cells including the first new cell by executing a rule check on the circuit design, (B) comparing the first report with a database comprising a plurality of second cells already manufactured and (C) notifying a client of the first new cell in response to the first new cell not matching any of the second cells.

Abstract: A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current electrical power dissipation mode (i.e., power mode) of the processor. The functional unit(s) respond to the power mode signal by altering their electrical power dissipation and issuing an acknowledge signal. The control unit receives a power mode input representing a request to enter a new power mode, and issues the power mode signal in response. The control unit waits for the acknowledge signal(s), and responds to the acknowledge signal(s) by modifying the one or more bits of the register to reflect the new power mode. A method is described for transitioning from a current power mode to a new power mode. A data processing system is disclosed including a peripheral device coupled to the processor.

Abstract: A computerized list is provided with auxiliary pointers for traversing the list in different sequences. One or more auxiliary pointers enable a fast, sequential traversal of the list with a minimum of computational time. Such lists may be used in any application where lists may be reordered for various purposes.

Abstract: A dynamic break loop capable closed loop network having a plurality of switches and links. Each switch has two uplink ports that each have a set of dynamic break loop logic functions that may be enabled or disabled. The dynamic functions include inserting an ID number of a source switch into each frame that is transmitted from the switch, enabling a transmit function of each uplink port to monitor the ID number of each frame, and enabling a receive function of each uplink port to monitor the ID number of each frame. If the ID number is not equal to a filter ID number, then the frame will pass unchanged. If the ID number is equal to the filter ID number, then the frame will be cut off and will not be allowed to pass. The dynamic functions create a dynamic break for each switch in the network. The result is a closed loop network that operates dynamically as a plurality of open loop networks.