Abstract: Multiple matches of words in a content addressable memory are detected by identifying each match of the input word to a word in the memory, and generating a representation of a relationship OR(xi AND xj), where xi=x1, x2, . . . , xN-1, xj?xi+1, xi+2, . . . xN, and x1, x2, . . . , xN are the compare results of the individual words in the memory to the input word. A representation of at least one match is identified by generating a representation of a relationship x1 OR x2 OR x3 OR . . . OR xN. The apparatus comprises a hierarchy of logic that carries a general match representation indicating at least one match between the input word and all of the memory words, and a multiple-match representation indicating multiple matches between the input word and the words in the memory.

Abstract: The present invention is directed to a system and method for data verification in a RAID system. A method of verifying data in a RAID system may include reading a first item of data from a first data storage device and a second item of data from a second data storage device. The first item of data from the first storage device is compared with the second item of data from the second storage device. If the first item of data does not match the second item of data, a third item of data is read from a third data storage device. The third item of data is compared with the first item of data and the second item of data.

Abstract: A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives requests from the multiple processors, each of the requests including information of a memory address. The memory controller selects one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and provides the requesting processor with a requested memory operation on the selected memory bank.

Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

Abstract: A system and method for communication amongst a device and multiple controllers. A controller may use a direct communication path to the device or may route the communication to another controller that has a faster communication path to the device. Such a system and method is particularly useful when the device takes a long time to switch from a communication path with the second controller to a communication path with the first controller.

Abstract: An improved semiconductor memory structure and methods for its fabrication are disclosed. The memory structure includes a semiconductor substrate having a dielectric stack formed over a channel region of a semiconductor substrate. The dielectric stack includes a layer of electron trapping material that operates as a charge storage center for memory devices. A gate electrode is connected with the top of the dielectric stack. In various embodiments the electron trapping material forms a greater or lesser portion of the dielectric stack. The invention includes a method embodiment for forming such a memory device.

Abstract: An apparatus comprising a processor and a translator circuit. The processor may (i) comprise a number of internal registers and (ii) be configured to manipulate contents of the internal registers in response to instruction codes of a first instruction set. The translator circuit may be configured to implement a stack using one or more of the internal registers of the processor.

Abstract: An integrated circuit design library includes a timing parameter representative of a design element in an integrated circuit; an area size parameter representative of the design element in an integrated circuit; and a routing demand parameter representative of a number of connections required for the design element for each value of the timing parameter and the area size parameter.

Abstract: A method of removing a hard mask layer from a patterned layer formed over an underlying layer, where the hard mask layer is removed using an etchant that detrimentally etches the underlying layer when the underlying layer is exposed to the etchant for a length of time typically required to remove the hard mask layer, without detrimentally etching the underlying layer. The hard mask layer is modified so that the hard mask layer is etched by the etchant at a substantially faster rate than that at which the etchant etches the underlying layer. The hard mask layer is patterned. The patterned layer is etched to expose portions of the underlying layer. Both the hard mask layer and the exposed portions of the underlying layer are etched with the etchant, where the etchant etches the hard mask layer at a substantially faster rate than that at which the etchant etches the underlying layer, because of the modification of the hard mask layer.

Abstract: A circuit for use in a data packet transmission system. The circuit generally comprises a buffer and a test circuit. The buffer may be configured to store a plurality of data packets. The test circuit may be configured to (i) monitor a number of the plurality of data packets in the buffer, (ii) permit an additional data packet to the plurality of data packets into the buffer responsive to the number being less than a first threshold, and (iii) discard the additional data packet in accordance with a probabilistic test responsive to the number being greater than the first threshold.

Abstract: A method and apparatus for generating a system specific test by providing sophisticated error tracking mechanisms to trigger on a specific system event. The present invention addresses the problem of monitoring network traffic and isolating a point of error at the testing stage. The present invention defines a specific system event to be monitored. A trigger is created in the host system and routed to the analyzer, wherein the trigger is used to allow the analyzer to capture information related to the specific system event. When a signal is received at the analyzer, the signal automatically triggers the analyzer to capture and store a predetermined amount of data related to the specific system event before and after the trigger is executed.

Abstract: The present invention is a method of acquiring phase lock to a data signal in a digital channel having a digital feedback loop. The method generally comprises: (A) applying the data signal to an analog phase lock loop configured to have (i) at least two poles and (ii) presend intermediate output signal frequency locked to the data signal; (B) applying the data signal and the intermediate output signal to the digital channel; and (C) adjusting a delay constant for the digital feedback loop to (i) compensate for variations in phase between the data signal and the intermediate output signal and (ii) acquire phase lock by using a single pole in the digital channel.

Abstract: A method includes steps of: (a) receiving as input a waveform of a transient signal as a function of time for an aggressor net; (b) finding a peak value of the waveform and a corresponding peak time of the waveform propagated from the aggressor net to a victim net; (c) defining a selected time interval within the waveform at the victim net that includes the peak value and excludes features of the waveform not associated with the peak value wherein the selected time interval begins at a first time and ends at a second time; (d) calculating a weighted value of a function of the waveform at the first time and the second time; (e) calculating a local average value of the waveform as a function of the peak value and the weighted value; and (f) generating as output the local average value of the waveform.

Abstract: A channel encoding system and a channel decoding system for use in transmitting multiple high definition television programs in a single satellite channel. The channel encoding system may comprise a frame formatter that may be configured to format a transport stream to produce a block stream. An error correction encoder may be configured to encode the block stream to produce an error protected block stream. An interleave module may be configured to interleave the error protected block stream to produce a data stream. A turbo encoder may be configured to encode the data stream to produce an encoded stream. A bit-to-symbol mapper may be configured to map the encoded stream to produce a symbol stream capable of at least eight different symbols. Finally, a modulator may be configured to modulate the symbol stream.

Abstract: The present invention is directed to a method and apparatus for optimizing fragmentation of integrated circuit boundaries for optical proximity correction (OPC) purposes. The present invention may balance the number of vertices and the “flexibility” of the boundary and may recover fragmentation according to the process intensity profile along the ideal edge position to obtain the best decision for OPC.

Abstract: The present invention is directed to a system and method for a multihost information handling system employing a static logical identifier. In an aspect of the present invention, at least one input/output interface has a target masking configuration utility of the input/output interface which controls the allocation of target devices to the host. Each host may have its own target masking configuration utility or may communicate with each other through agents connected to each other through a network such as a local area network. A controller is communicatively coupled to the ports. When the controller receives an identifier from the host, the controller generates a logical identifier from the identifier, the logical identifier suitable for being utilized in conjunction with a look-up table to provide access to the target.

Abstract: Embodiments of the invention include a method for forming alternating aperture phase-shift masks. An optically transparent substrate suitable for having a pattern of phase-shift regions formed thereon is provided. Alternatively, an opaque pattern is formed on the optically transparent substrate, the opaque pattern defining a pattern of phase-shift regions on the substrate. The phase shift regions are then ion implanted to damage the phase-shift regions. The damage penetrates to a predetermined depth and forms damaged regions that can be more easily etched than the adjacent undamaged portions of the substrate. The damaged portions define a final profile for phase shift recesses to be formed in the substrate. After implantation, substrate material is removed from the damaged phase-shift regions so that recesses are formed therein. The recesses are formed having a depth that corresponds to the depth of the damage caused in the phase-shift regions by the ion implantation.

Abstract: An original netlist is transformed to one employing universal gates. A negation net is created for each net coupled to an input or output of each gate and an input of each inverter in the original net. Each gate is removed from the original netlist and a universal gate is inserted so that the nets previously coupled to the inputs and output of the removed gate and a negation of those nets are coupled to the inputs and outputs of the inserted universal gate in a selected arrangement. Each inverter is removed from the original netlist and the net previously coupled to the input of the inverter is negated. A universal gate comprises gates performing anding and oring functions whose inputs and outputs are selectively coupled to the nets of the original netlist, and their negations.

Abstract: A semiconductor device comprising one or more diffused memories and one or more diffused regions. The one or more diffused regions may be configured to provide one or more ports for the one or more diffused memories.

Abstract: Two sets of disk drives are mounted in a grid arrangement onto a backplane to form a removable multi-disk drive unit for a high capacity disk storage system. The removable units may be mounted into an enclosure that contains a RAID controller. The disk drives are mounted such that the longest edge of the disk drive is perpendicular to the plane of the backplane.