Abstract: A method of recovering from loading invalid data into a register within a pipelined processor. The method comprises the steps of (A) setting a register status for the register to an invalid state in response to loading invalid data into the register and (B) stalling the processor in response to an instruction requiring data buffered by the register and the register status being in the invalid state.

Abstract: A design and verification aide that can be used to produce BZ codes under static or dynamic process, voltage, temperature and external reference resistor (PVT and R) conditions for impedance controlled buffers or any other application using BZ codes. The simulation technique follows that of a flash ADC, and effectively replaces an awkward state-machine BZ controller with a subcircuit consisting of 5 BZREFN's, 5 BZREFP's, 10 HSPICE behavioral comparators, and the BZVREF. The resulting N- and P-codes may be adjusted by a parameterized dither count with minimum and maximum code values enforced by the model, and the comparators can be modified to model offset voltage.

Abstract: A low-k interconnect dielectric layer is strengthened by forming pillars of hardened material in the low-k film. An E-beam source is used to expose a plurality of pillar locations. The locations are exposed with a predetermined power and exposure time to convert the low-k film in the selected locations to pillars having higher hardness and strength than the surrounding portions of the low-k film.

Abstract: A self-timed scan circuit includes a multiplexer for selecting either a data input or a test input in response to an internal test enable signal and for generating a multiplexed output; a latch coupled to the multiplexer for generating a latched output in response to a next clock pulse; and a timing control circuit for generating the internal test enable signal in response to a global test enable signal wherein the internal test enable signal is set to logic one when the global test enable signal is set to logic one and wherein the internal test enable signal is set to logic zero in response to the next clock pulse.

Abstract: A method and control system for detecting harmonic oscillation in a chemical mechanical polishing process and reacting thereto, such as by taking steps to at least one of: 1) reduce or eliminate the harmonic oscillation; and 2) counter the noise which is associated with the harmonic oscillation. By reducing or eliminating harmonic oscillation, films with reduced structure strengths including low k dielectric films can be used. By countering the noise, the quality of the work environment is improved.

Abstract: The present invention is a method for operating a computer-based accounts payable system. The user inputs a bill that includes a billing code. The system then determines whether the billing code is present in the budget database. If the billing code is present in the budget database, the system approves payment of an amount associated with the billing code in the budget database. If the billing code is not present in the budget database, the system approves payment of a budget amount associated with the billing code in a default budget database. In the preferred embodiment, the system also checks whether a particular task has been completed before approving payment of said bill, and checks to insure that a previous bill covering the same task has not been paid previously.

Abstract: The present invention is directed to an interface. An interface system suitable for coupling a first bus interface controller with a second bus interface controller includes a first bus interface controller and a second bus interface controller in which the second bus interface controller is coupled to the first bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data.

Abstract: Optical emission spectra from a test wafer during a plasma process are measured using a spectrometer. The plasma charging voltage retained by (detected by) the test wafer is measured after the process step is completed. The emission spectra are correlated with the plasma charging voltage to identify the species contributing to the plasma charging voltage. The optical emission spectra are monitored in real time to optimize the plasma process to prevent plasma charging damage. The optical emission spectra are also monitored to control the plasma process drift.

Abstract: A method and apparatus for reducing block related artifacts in video are disclosed. A boundary is defined in a video frame between at least two or more sub-blocks where each of the sub-blocks contains a predetermined number of pixels. Pixels adjacent to the boundaries of the sub-blocks may be filtered to reduce blocking artifacts in the video. Pixel video values such as luma and chroma values may be utilized as input values to an anti-block filter. Average mean and average variance of the pixel video values in a sub-block are used to determined when anti-block filtering is applied. Pixels adjacent to the sub-block boundaries are filtered with an anti-block filtering algorithm in the event a predetermined condition is satisfied where the condition may be based upon the calculated average mean and average variance values. The filtering algorithm may include recalculating a pixel video value for pixels adjacent the sub-block boundaries.

Abstract: A system and method for cooling a series of heat generating devices arrayed sequentially in the axis of flow for a cooling medium. An inlet manifold contains a stepped chamber whereby cool air is apportioned to several chambers, each chamber containing a heat generating device. An outlet manifold contains a similar stepped chamber whereby heated air is exhausted from the heat generating device. In an embodiment of a disk array, each chamber may hold one or more disk drives. Further, the manifold system may also serve as a mounting bracket for the disk drives.

Abstract: In contrast to prior are solutions that conduct an averaging operation to estimate metrics related to a communications channel such as a signal-to-noise ratio, the present invention selects a particular value such as a minimum, maximum, or median value from a distribution of values collected over a selected interval. Selecting a particular value from the distribution of values facilitates a more accurate characterization process and increased data throughput. To reduce the processing burden associated with selecting a particular value, the present invention provides a set of cascaded value selection queues that each selects a particular value from the queued values such as a minimum value. The cascaded queues are also successively sub-sampled to reduce the computing resources required to characterize the communications channel. The estimated metrics resulting from the above-described process may be used to adjust the data encoding process and increase data throughput on the communications channel.

Abstract: A line driver couples a data transceiver to a transmission line having a load impedance Z via a transformer with a turns ratio of 1:n, the data transceiver transmitting signals in a first frequency range and receiving signals in a second frequency range different from the first frequency range. The line driver includes an input port for receiving an input signal voltage, an output port for supplying an output signal voltage to the transformer, and a differential amplifier having a low pass filter for amplifying the input signal voltage and outputting an amplified signal voltage. The line driver further includes termination resistors having a resistance Rt, where R t = Z 2 ? n 2 × k ( 0 < k ? 1 ) , and a positive feedback path for coupling the output signal voltage from the output port to an appropriate node of the differential amplifier so that a synthesized output impedance substantially matches the load impedance Z over the second frequency range.

Abstract: A system generally having a first circuit, a second circuit, and a pair of non-crossing conductive paths. The first circuit may be configured to convert between (i) a serial signal on a first differential interface and (ii) a parallel signal. The pair of non-crossing conductive paths may connect the first differential interface with a second differential interface. The second circuit may be configured to invert the parallel signal in response to a control signal in an inverting state.

Abstract: Nanotube memory cells are formed on a semiconductor substrate. Lower and upper memory cell chambers are formed by forming a first trench overlying the first and second contacts in a nitride layer, forming a second trench overlying the first and second contacts in a dielectric layer, depositing a nitride layer on the combined lower and upper chambers, and patterning the nitride layer to form an access hole to the nanotube layer and a second access hole to the second contact. A conductive layer is then deposited and patterned to form a top electrode contact and a nanotube layer contact. The conductive material closes the aperture created by the access hole.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first portion of an output data stream in response to a first portion of an input data stream. The second circuit may be configured to present a second portion of the output data stream in response to a second portion of the input data stream. The apparatus may be configured to perform color and gamma correction on the input data stream to generate the output data stream in response to one or more control signals. In one example, the apparatus may comprise block move engine (BME).

Abstract: A multiple port system includes a plurality of port devices, each port device including a control register set, and a control bus coupled to the plurality of port devices. The control bus provides a control signal to each port device, and the control signal includes port address information and register address information. The control register set includes a set of registers responsive to the control signal if the port address information indicates the corresponding port device, and a designated register responsive to the control signal if the port address information indicates one of the plurality of the port devices and the register address information indicates the designated register.

Abstract: A method for forming a dual damascene interconnect in a dielectric layer is provided. Generally, a first aperture is etched in the dielectric. A poison barrier layer is formed over part of the dielectric, which prevents resist poisoning. A patterned mask is formed over the poison barrier layer. A second aperture is etched into the dielectric layer, wherein at least part of the first aperture shares the same area as at least part of the second aperture.

Abstract: A method for manufacturing hemi-cylindrical and hemi-spherical micro structures is provided. A pattern is formed onto a substrate, and a layer of material is subsequently grown onto the substrate. Due to growth characteristics, the layer will form radially symmetric features when grown to an appropriate thickness.

Abstract: An arrangement for controlling the transmission of a light signal is disclosed. The arrangement includes a first fiber optic line for transmitting the light signal and a light receiving unit operatively coupled to the first fiber optic line so that the light signal is received by the light receiving unit. The light receiving unit is operative to refract the light signal so that the light signal is substantially prevented from being transmitted through the light receiving unit if an intensity level of the light signal has a predetermined relationship with an intensity threshold level.

Abstract: Automated photolithography of integrated circuit wafers is enabled with a processor connected to a Rayleigh derator, a form factor generator, a logic synthesizer, a layout generator, a lithography module and a wafer process. The Rayleigh derator receives manufacturing information resulting from yield data in the wafer process, and this manufacturing data is then used to derate the theoretical minimum feature size available for etching wafer masks given a known light source and object lens numerical aperture. This minimum feature size is then used by a form factor generator in sizing transistors in a net list to their smallest manufacturable size. A logic synthesizer then converts the net list into a physical design using a layout generator combined with user defined constraints. This physical design is then used by the mask lithography module to generate wafer masks for use in the semiconductor manufacturing.