Abstract: Disclosed is a system and method employing a magnetic proximity switch to enable the transfer of power between a power supply unit and a docking unit or to transfer data between a docking unit and a peripheral module such as a disk drive or controller module. Power may be transferred through the switch, or a signal from the switch may be employed to enable a control circuit. The control circuit may control a plurality of voltages or currents and may ramp voltages or currents to limit surge current when a module is installed or removed. The control unit may also be employed to place data and control signals in a high impedance state when a module is not docked, limiting electromagnetic radiation.

Abstract: Embodiments of the invention include an apparatus for uniformly contaminating samples. The apparatus includes a housing that contains a rotatable carousel for the holding samples. A drive element is used for rotating the carousel. The apparatus includes a contaminant dispenser for dispersing a contaminant onto the samples. The apparatus also includes a control element that can be used to control contaminant dose and carousel rotation rate and rotation time. A method for uniformly contaminating samples includes providing such a contamination chamber and placing a plurality of samples within the chamber. A contaminant is introduced into the chamber and the samples are spun so that the contaminant is uniformly distributed onto the spinning samples. After contamination the samples are removed from the chamber.

Abstract: A substrate having a core with vias disposed therein. A reference layer is formed on the core, with voids in the reference layer that are formed around the vias in the core. Traces on a routing layer overlie the reference layer. Also included is a contact layer with contacts disposed in a contact pattern. The core is logically divided into sections, and the vias within a given one of the sections are aligned in rows substantially along a first direction. At least a portion of the vias are not aligned with the contact pattern. The voids in the reference layer within the given one of the sections are also aligned in rows substantially along the first direction and aligned with the vias. Further, the traces within the given one of each of the sections are also aligned substantially along the first direction between the rows of voids, and not substantially overlying the rows of voids.

Abstract: A signal deskew circuit is provided, which includes first and second signal branches, each branch extending between a start location and a respective end location. Each signal branch includes a send path and a return path, which have substantially the same propagation delays. An adjustable delay buffer is coupled in the send and return paths of a first of the signal branches and has a delay, which is adjustable based on a respective adjust signal. A skew sensor coupled to the return paths of the first and second signal branches, which generates the respective adjust signal for the adjustable delay buffer based on a phase difference between signals on the return paths of the first and second signal branches.

Abstract: An apparatus for controlling the substrate temperature of a substrate during processing of the substrate at a process energy. A chuck temperature input receives temperature measurements from temperature sensors at a substrate chuck, and a temperature set point input receives temperature set points. The temperature set points define a range of temperatures within which the apparatus maintains the substrate temperature. A chuck temperature controller output sends control signals to a chuck temperature controller, which signals are operable to selectively increase and decrease the chuck temperature. A process energy output sends control signals that are operable to selectively increase and decrease the process energy during the processing of the substrate. A controller compares the temperature measurements received from the temperature sensors at the substrate chuck through the chuck temperature input to the temperature set points received through the temperature set point input.

Abstract: A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.

Abstract: A circuit dynamically biases switching elements in a current-steering digital-to-analog converter (DAC), The DAC includes, in each cell, a current source coupled to a current node, a first switching element coupled between the current node and a first DAC output node, and a second switching element coupled between the current node and a second DAC output node. The circuit includes first and second inputs coupled to the first and second DAC output nodes, respectively, first and second outputs coupled to the first and second switching elements, respectively, and a third output coupled to the first and second switching elements. The first and second outputs provide a first ON bias voltage and a second ON bias voltage to control the first and second switching elements, respectively, such that a voltage at the current node is maintained at a predetermined voltage. The third output provides a common OFF bias voltage.

Abstract: A profile-based system is described for verifying the functionality of a device design. In one embodiment, the system includes a profile generation module, a coverage measurement module, and a pattern generation module. The profile generation module operates from a rule set that represents the design specification and any applicable standards, and a profile mode that specifies “interesting” aspects of test patterns for device design verification. The profile generation module determines an ordered set of variable values that specify a test pattern, and produces a profile that intelligibly describes the interesting aspects of the test pattern. The coverage measurement module analyzes the profile to determine coverage, and the analysis results may be operated on by the profile generation module to determine a profile for an improved test pattern. The pattern generation module converts the profile into a test pattern having the interesting aspects specified in the profile.

Abstract: A circuit generally comprising a first memory, a second memory and a processor is disclosed. The first memory may store an instruction to read an updated security value of at least three security values. The second memory may store (i) the updated security value and (ii) information related to security of the circuit. The processor may be configured to (i) execute the instruction while a register stores a highest security value of the security values, (ii) copy the information from the second memory to a third memory in response to the update security value being greater than a current security value of the security values stored in the third memory and (iii) ignore the information in the second memory in response to the updated security value being no greater than the current security value.

Abstract: A loop of delayed read commands is established from a larger set of queued commands. Upon recognizing a delay in completing a first read command which is followed by a second read command, the loop is established by setting loop start pointer to identify the first delayed read command and setting a loop end pointer to identify the second read command. Upon recognizing a delay in completing the second read command which is followed by a third read command, the loop end pointer is advanced to identify the third read command. All of the read commands in the loop at and between the loop start pointer and the loop end pointer are completed before attempting to complete other commands in the queue not within the loop.

Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

Abstract: In a crosspoint switch, both input buses and output buses are driven at low swing. Self-timed, differential, push-pull, low swing driver circuits drive the input buses and are provided in the crosspoints to drive the output buses. Clocked, regenerative sense amplifiers are provided in crosspoints and at outputs of the data buses.

Abstract: A method for monitoring polishing process parameters for an integrated circuit structure on a substrate. A first metrology site is constructed on the substrate. The first metrology site represents a design extreme of a high density integrated circuit structure. The first metrology site is formed by placing a relatively small horizontal surface area trench within a relatively large surface area field of a polish stop material. A second metrology site is also constructed on the substrate. The second metrology site represents a design extreme of a low density integrated circuit structure. The second metrology site is formed by placing a relatively large horizontal surface area trench within a relatively small surface area field of a polish stop material. The substrate is covered with a layer of an insulating material, thereby at least filling the trenches.

Abstract: A method, system, and a computer program product to provide correct and complete input into a shell generation tool that provides the infrastructure for design and development of an integrated circuit. Given a definition of a platform, in part a partially manufactured semiconductor product having some diffused and some configurable resources, a user can enter data that is correct and complete into the shell generation tool using several techniques. The tool itself can present data for the user to select that is complete and correct, i.e., the data, inter alia, has no syntactic or other errors of an HDL, satisfies the constraints and naming conventions required by the tool, a customer of the semiconductor product, and/or the entity designing the product, provides appropriate timing and voltage levels, and is otherwise compatible with other data in the generation tool.

Abstract: An improved method of operating a digital signal processor instruction pipeline and a memory interface for implementing the method. Memory store requests are separated into an address phase and a data phase. Store addresses are issued to the interface when ready and held in a queue until the corresponding store data is available. The store data is issued to the interface and held in a queue until its corresponding store address is to be coupled to memory. The pipeline operates more efficiently because it does not have to wait for store data before issuing the address and related control signals. Data coherency is maintained because load and store addresses are issued at the same pipeline stage and executed in the order issued.

Abstract: A scan chain comprising a series of flip-flops and two clock signals, where each clock signal is coupled to alternating flip-flops in the series. The second clock signal is typically 180 degrees out of phase with the first clock signal. The two clock signals may be generated from a base clock signal that is coupled to two clocking devices. The first clock signal is output from one clocking device and the second clock signal is output from the other. One clocking device typically passes the base clock signal without delay and the second typically delays it. The clocking devices may be MUXes that can be switched to place the clock signals in or out of phase. The scan chain can be incorporated within an integrated circuit wherein the clock signals are out of phase during testing of the integrated circuit and are in phase after testing of the integrated circuit is complete.

Abstract: A system and method are provided for forming a multi-chip package. The multi-chip package includes a multi-layer substrate and a heat spreader of single, unibody construction. At least two integrated circuits are coupled between the multi-layer substrate and the heat spreader. The integrated circuits are spaced from one another to allow airflow between those circuits and a portion of the underside surface of the heat spreader. Depending on the layout of the package, a passive device can also be placed in the space between integrated circuits. The passive device extends upward a spaced distance from the underneath surface of the heat spreader so as not to block the airflow therebetween. The multi-chip package can accommodate integrated circuits that are either all packaged, all unpackaged, or a combination of each.

Abstract: A thermal measurement device for obtaining accurate thermal profiles during flip-chip semiconductor packaging and methodologies for making such devices is disclosed. Particularly, a measurement device comprised of a thermocouple sandwiched between a semiconductor packaging substrate and a semiconductor die. Such a device providing increased accuracy in temperature measurement. The present invention also teaches a packaging substrate assembled with a semiconductor die having an opening in the substrate enabling the placement of a thermocouple such that it is in contact with the die and secured in place. Additionally, methods of constructing the devices of the present invention are disclosed.

Abstract: The present invention is a method and system for providing a scalable memory building block device. The memory building block device includes a plurality of separate memory arrays, decode logic for selecting only one bit from the plurality of memory arrays, and output means for providing only one bit as an output of the memory building block device, such that the memory building block device generates as its output only one bit.

Abstract: An integrated circuit with a pressure resistant current carrying structure having electrically conductive layers for carrying current. A first electrically nonconductive material at least partially surrounds the electrically conductive layers, and provides electrical insulation between the electrically conductive layers. The first electrically nonconductive material has a first degree of fragility and a first dielectric constant. A second electrically nonconductive material is disposed in a pattern within the first electrically nonconductive material and between the electrically conductive layers, and provides structural support for the first electrically nonconductive material between the electrically conductive layers. The second electrically nonconductive material has a second degree of fragility that is less than the first degree of fragility and a second dielectric constant that is greater than the first dielectric constant.