Patents Assigned to LSI Logic
  • Method and structure for creating ultra low resistance damascene copper wiring
    Patent number: 6987059
    Abstract: A low resistance copper damascene interconnect structure is formed by providing a thin dielectric film such as SiC or SiOC formed on the sidewalls of the via and trench structures to function as a copper diffusion barrier layer. The dielectric copper diffusion barrier formed on the bottom of the trench structure is removed by anisotropic etching to expose patterned metal areas. The residual dielectric thus forms a dielectric diffusion barrier film on the sidewalls of the structure, and coupled with the metal diffusion barrier subsequently formed in the trench, creates a copper diffusion barrier to protect the bulk dielectric from copper leakage.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: January 17, 2006
    Assignee: LSI Logic Corporation
    Inventors: Peter A. Burke, Hongqiang Lu, Sey-Shing Sun
  • Digital clock recovery PLL
    Patent number: 6987817
    Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: January 17, 2006
    Assignee: LSI Logic Corporation
    Inventor: David R. Reuveni
  • Macroblock level intrarefresh technique for encoded video
    Patent number: 6987805
    Abstract: A method is provided for encoding K>1 sequentially presented video pictures. Each of the K pictures is divided into an m>1 row×n>1 column array of non-overlapping coding units of equal sizes. Each coding unit occupies a respective coding unit position in the picture from which it was divided. An arbitrary, pseudo random pattern of coding units is selected for refreshing during each of the K pictures. Each pattern selected during any given one of the K pictures includes a sequence of one or more coding units of the array. In addition, the pixels of each coding unit selected for refreshing during a kth picture occupy different pixel positions than each coding unit selected for refreshing during a preceding one of the 1st to (k?1)th pictures of the K pictures. Furthermore, each pixel position of a moving picture image formed from the K pictures is selected for refreshing once over the sequence of K pictures.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: January 17, 2006
    Assignee: LSI Logic Corporation
    Inventors: Charles Weckel, Hervé Brelay, Feng-Ming Wang
  • Yield driven memory placement system
    Publication number: 20060010092
    Abstract: A user-defined memory design is mapped to memories of a base platform for an IC that contains a plurality of memory sets, each containing a plurality of memories of a predetermined type. An optimal memory set is selected from the plurality of memory sets for the design by selecting a preference rate for each memory set from the plurality of sets based on the design and its connections to portions of the IC, and selectively assigning the design to one of the memory sets based on the preference rate. The design is optimally mapped to a plurality of memories of the selected memory set by defining an index of the position of each customer memory in the selected memory set. The customer memories in the selected memory set are arranged in an order, and successive numbers of memories of the selected memory set are assigned to each customer memory in order.
    Type: Application
    Filed: June 23, 2004
    Publication date: January 12, 2006
    Applicant: LSI Logic Corporation
    Inventors: Alexander Andreev, Andrey Nikitin, Ranko Scepanovic
  • High performance diode implanted voltage controlled p-type diffusion resistor
    Patent number: 6984869
    Abstract: The present invention provides a diffusion resistor that is formed in the substrate. A diffusion region is formed within the substrate that contains first and second contact regions extending downward from the surface of the substrate. Third and fourth contacts are also located within the diffusion region between the first and second contacts and define a conduction channel therebetween. This contact also extends downward from the surface of the substrate. These contacts are connected to metal layers. The first and second contacts form the two ends of the diffusion resistor; the third and fourth contacts connect to N+p? diodes such that application of a voltage to these contacts forms respective depletion regions within the diffusion region. The depletion regions change in size depending on the voltage applied to their respective contact, thereby changing the resistance of the depletion resistor.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Sean Christopher Erickson, Kevin Roy Nunn, Jonathan Alan Shaw
  • Method of mapping logic failures in an integrated circuit die
    Patent number: 6986112
    Abstract: A method of mapping logic failures in an integrated circuit die includes generating a navigation map of test paths for an integrated circuit die, selecting a grid spacing to define a grid map of cell locations from the navigation map for each of the test paths, and calculating a value for each of the cell locations that is representative of the difference between a total number of the test paths intersecting each of the cell locations and a failed number of the test paths intersecting each of the cell locations.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Bruce Whitefield, Joseph Cowan
  • Methods and structure for dynamic modifications to arbitration for a shared resource
    Patent number: 6985985
    Abstract: Methods and structure for enhanced flexibility in bus arbitration without requiring modification to a standard arbiter circuit. Parameters for determining the priority of each channel involved in the arbitration are provided to a computational element to apply predicate functions thereto and thereby generate an index value. The index value is then used to access the lookup table for that channel to determine the present priority of the channel in an arbitration structure. The use of a lookup table permits simple modification to the arbitration structure for a particular application. The predicate evaluation of selected parameters further enhances flexibility in adapting the arbitration structure to the requirements of a particular application.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventor: Robert W. Moss
  • Method of reducing miscorrections in a post-processor using column parity checks
    Patent number: 6986098
    Abstract: The present invention is a method and system for reducing miscorrections of data in a post-processor. In an embodiment of the invention, the system and method may compare a result of an exact match function and a metric for each row of a reconstructed data block to determine if a correction should be made. An algorithm for performing an exact match function may include a column parity check syndrome, a matched filter error syndrome, and an error mask of the present invention. If a result of an exact match function is an exact match, a priority of correction may be given to the row in which the exact match was produced.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Alan D. Poeppelman, David L. Schell, Kevin G. Christian
  • Method and/or apparatus for SCSI target verification
    Patent number: 6986083
    Abstract: A method for data verification in a data storage environment including the steps of (A) sending a command from an initiator to a target, where the command defines an expected data pattern, (B) sending a block write command from the initiator to the target, where the write command initiates sending data from the initiator to the target, (C) comparing data received to the expected data pattern and (D) generating a status indication in response to the comparison.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: January 10, 2006
    Assignee: LSI Logic Corporation
    Inventors: Carl E. Gygi, Mark A. Slutz, Stuart L. Nuffer
  • Object code configuration tool
    Publication number: 20060005167
    Abstract: A system and method for managing several versions of a device with embedded object code by using an editor to scan the object code, find a signature, change one or more parameters within the object code, and replace the object code. The device may be shipped to a customer in a standard configuration and the object code may be changed by the customer using the editor.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Applicant: LSI Logic Corporation
    Inventor: Roy Wade
  • Re-configurable content addressable/dual port memory
    Patent number: 6982891
    Abstract: A re-configurable core cell is provided that can be used as either a content addressable memory cell or a dual-ported static read only memory cell. The re-configurable core cells are pre-diffused on the chip. The core cells may then be configured as CAM or SRAM with a metal layer. The peripheral logic of the CAM or SRAM may be built from gate array devices.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventor: Carl Anthony Monzel, III
  • Write compensation for data storage and communication systems
    Patent number: 6982939
    Abstract: Methods and systems for write compensation for optimizing the performance of a data storage or communication channel are disclosed. In one embodiment, a method comprises determining channel sensitivity to modifications in write signal parameters, detecting systematic errors in a read signal recovered from data written with a first set of write parameters, and adjusting the write signal parameters by an amount determined from the channel sensitivity such that the systematic errors are reduced when data are written with the adjusted write parameters.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Judith C. Powelson, David K. Warland, Ian E. Harvey, Yung-Cheng Lo, Christine Pepin, Steven R. Spielman, Ting Zhou, Jonathan A. Zingman
  • Method and system for symbol binarization
    Patent number: 6982663
    Abstract: The present invention is directed to an improved method for the binarization of data in an MPEG data stream. The invention makes use of unary binarization to create codewords up until an index threshold. Once the threshold has been met, succeeding code symbols have appended to them an exp-Golomb suffix. This hybrid binarization scheme reduces the number of binary codewords to be processed by a Binary Arithmetic Coder (BAC), thus reducing the computation required by the BAC.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventor: Lowell Winger
  • Ion recoil implantation and enhanced carrier mobility in CMOS device
    Patent number: 6982229
    Abstract: An integrated circuit (IC) includes a CMOS device formed above a semiconductor substrate having ions therein that are implanted in the semiconductor substrate by an ion recoil procedure. The IC preferably, but not necessarily, incorporates sub-0.1 micron technology in the CMOS device. The implanted ions may preferably be germanium ions. A strained-silicon layer is preferably, but not necessarily, formed above the ion-implanted layer of the semiconductor substrate. The strained-silicon layer may be formed by a silicon epitaxial growth on the ion-implanted layer or by causing the ions to recoil into the semiconductor substrate with such energy that a region of the semiconductor substrate in the vicinity of the surface thereof is left substantially free of the ions, thereby forming a strained-silicon layer in the substantially ion-free region.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Agajan Suvkhanov, Mohammad R. Mirabedini
  • High speed OC-768 configurable link layer chip
    Patent number: 6983342
    Abstract: An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Victor Helenic, Clinton P. Seeman, Danny C. Vogel
  • Mechanism for improving the structural integrity of low-k films
    Patent number: 6982206
    Abstract: According to one embodiment, a method of forming a low-k dielectric composite film is provided. A low-k interconnect dielectric layer is strengthened by forming whiskers in the low-k film. The whiskers are formed simultaneously with the low-k layer. In one embodiment, the low-k structure is removed by heating a volatile matrix film, leaving a whisker residue.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, Steven E. Reder, Hemanshu Bhatt
  • Programmable digital filter implementation for loss-of-signal detection for serial communications applications
    Patent number: 6983299
    Abstract: A circuit generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) detect a state of an input signal and (ii) present a plurality of intermediate signals each representative of the state of the input signal during a plurality of clock cycles. The second circuit may be configured to present a filtered signal in response to a selected number of the intermediate signals having a predetermined state.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: January 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Christopher D. Paulson, Steven A. Schauer
  • Optimization of die yield in a silicon wafer “sweet spot”
    Patent number: 6980917
    Abstract: A method of increasing the wafer yield for an integrated circuit includes the steps of receiving as input a shot map, an initial orientation of a center of the shot map relative to a center of a wafer resulting in a maximum number of printable die, a usable wafer diameter, a selected yield margin, and historical yield information for each die location in the shot map; generating a plot of an estimated yield for each die location in the wafer from the historical yield information; plotting an estimated wafer yield within an area of the wafer as a function of a radius; and selecting a sweet spot radius corresponding to an area of the wafer having a wafer yield that is substantially equal to the selected yield margin for finding an offset from the initial orientation of the center of the shot map that results in a maximum wafer yield.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: December 27, 2005
    Assignee: LSI Logic Corporation
    Inventors: Mark Ward, David Abercrombie, Larry Kelley
  • Integration of video processing into a block move engine
    Patent number: 6980217
    Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first output data stream in response to a first one or more of the data streams. The composite circuit may be configured to generate a combined output data stream in response to the first output data stream and remaining data streams.
    Type: Grant
    Filed: September 21, 2001
    Date of Patent: December 27, 2005
    Assignee: LSI Logic Corporation
    Inventor: David N. Pether
  • Method and apparatus to add slurry to a polishing system
    Patent number: 6979251
    Abstract: A semiconductor wafer is wetted with slurry by injecting the slurry into at least one channel which is provided in a wear ring, while the wear ring is holding the wafer and is pressed against a polishing pad. Preferably, the channel in the wear ring includes a plurality of outlets, and the outlets provide that the slurry can exit the wear ring and contact the polishing pad. Providing that the wear ring includes at least one channel and that slurry is injected into the channel during the polishing process provides that slurry is introduced between the wear ring and the polishing pad and this greatly increases the amount of slurry getting to the wafer.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: December 27, 2005
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman