Abstract: A receiver circuit is provided on an integrated circuit. The receiver circuit includes first and second power supply terminals, a ground supply terminal, a resistive element coupled between the first and second power supply terminals, and a receiver biased between the second power supply terminal and the ground supply terminal. The receiver draws a bias current through the resistive element, which varies as a positive function with a voltage on the second power supply terminal. The voltage on the second power supply terminal varies as an inverse function of the bias current.

Abstract: A system and method for communicating an image to a removable media device includes communicating the image from an image capture device to the removable media device over a wireless connection. The communicated image is stored in memory on the removable media device, and the stored image is deciphered. The deciphered image is recorded on removable media, the recorded image capable of being accessed on removable media device. In an additional aspect of the present invention, a method for communicating and formatting an image from an image capture device includes initiating a connection between an image capture device and an image storage device and querying the image storage device for a supported format. If the supported format differs from an image format, the image is deciphered to the supported format and communicated from the image capture device to the image storage device.

Abstract: A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.

Abstract: Systems and methods for generating, maintaining, and using merged partitions to process requests of one or more host systems to storage partitions of one or more storage elements. Each merged partition maps to one or more storage partitions defined within one or more of the storage elements. The storage elements may be combined to form a storage complex. Each storage element of the storage complex may include one or more storage volumes, such as an array of storage volumes. A system includes a map processor and an interface controller. The map processor is configured for mapping the storage partitions of each storage element to generate one or more merged partitions. The interface controller is communicatively connected to the host systems and to the map processor for processing the requests of the host systems to the storage volumes based on the merged partitions.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: A mechanism is provided for detecting new devices added to a Fiber Channel adapter. When a device is added to a connector, the mechanism generates a device detect signal for that port. The Fiber controller receives device detect signals for the existing ports and generates port select signals to configure the port bypass. The controller may then simply poll the device detect signals in an internal register to automatically detect a new device being added or a device being removed without breaking the loop and without a high software overhead.

Abstract: A method and system for designing a dummy grid in an open area of a circuit adjacent to at least one metal line comprising the circuits is disclosed. The method and system include patterning dummy lines in the dummy grid adjacent to metal signal lines, and patterning non-floating dummy lines in the dummy grid adjacent to metal power lines. The method and system further include varying sizes and spacing of the dummy lines in the respective columns of the dummy grid based on the distance between each column and the adjacent metal line, to achieve a balance between planarization and performance.

Abstract: A plurality of user-defined memories are mapped to pre-defined basic memories, such as defined on a base platform. The user-defined memories are dividing into classes of similar memories. A mapping technique is selected for members of a selected class of user-defined memories that minimizes the ratio (maxi,j(USEDi,j/AVAILi,j)) of basic memories that have been mapped to basic memories that are available for mapping. If the number of different memory mappings is smaller than a threshold the mapping technique is applied to each user-defined memory. If the number of different memory mappings is greater than the threshold, the groups are arranged in ordered queues of single memory types based on a mapping price and the mapping technique is selected based on a memory of each group and is applied to each user-defined memory in the respective group.

Abstract: Cells are placed into an integrated circuit floorplan by creating clusters of cells in modules, each cluster being composed of cells in a path connected to at least one flip-flop in the module, or of cells that are not in a path connected to any flip-flop. Regions are defined in the floorplan for placement of modules, and the clusters are placed into optimal locations in modules and placing the modules into optimal locations in the regions. T coordinates for the wires, modules and clusters are selectively recalculated. The clusters are moved in the floorplan for more uniform density, and the modules are assigned to regions based on module coordinates.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: Disclosed is a method for continuing a rebuilding process of a RAID system by flagging a block of data as being bad when a media error or other error occurs that prohibits the reconstruction of data. The block of data may be flagged by writing a bad error correction code to the block of data, by keeping a log of bad blocks of data, or by otherwise indicating that the block of data is known bad.

Abstract: The present invention is an integrated circuit containing multiple digital signal processors (DSPs). A single host processor interface is also placed on the chip to connect the multiple DSPs to the host. A separate direct memory access (DMA) unit is provided for each DSP to facilitate flow of data to and from a data memory for each DSP. Each DSP also includes an instruction memory.

Abstract: A region on a substrate contains multiple transistors in parallel that share a single salicided polysilicon gate electrode. Above or below the gate electrode are formed multiple plugs of refractory material along the length of the gate electrode. The multiple plugs of refractory material electrically interconnect the gate signal line and the salicided polysilicon gate electrode. The plug material is selected to minimize the work function between it and the salicided polysilicon gate electrode.

Abstract: Methods and systems are provided for thermal self-monitoring of integrated circuits. Temperature is sensed, digitized, encoded, and compared to one or more threshold values by circuits added within an integrated circuit. A signal produced by a thermal diode within an integrated circuit is applied to an analog to digital converter and may be compared to one or more threshold values to produce a digital over temperature condition signal. An appropriate cooling action may be initiated by processing of the digital signal so produced. Also provided are methods and systems to alter the range and resolution of the temperature threshold comparisons.

Abstract: A register address generation tool is used during the design of semiconductor products. For those registers and/or memories that are addressable on a bus, the register address generation tool creates the interconnect RTL, header files, static timing analysis constraint files, and verification testcases. The tool also maintains coherence between what has been generated and the available resources for the design of the semiconductor product in a design. If there are any registers and/or memories that are not being used, the register address generation tool may further generate the RTL that will convert these unused resources to performance-enhancing features such as control registers, status registers, etc. The register address generation tool read a design database having an application set to determine what hardmacs and what transistor fabric is available. It also receives as input a bus specification and address parameters.

Abstract: An apparatus comprising a media access controller (MAC), a configurable packet switch, and a network protocol stack in silicon. The network protocol stack may be configured to couple the media access controller to the configurable packet switch.

Abstract: A footprint based optimal characterization of intellectual property (IP) for more deterministic physical integration. The physical integration characteristics are based upon IP physical integration at an anchor point in a pre-defined IC platform. IP footprint characteristics are identified as fixed, variable or prioritized to each other, and bounding constraints are defined based on a set of characteristics for the IP, the platform characteristics and IC design requirements. The IP is physically synthesized using the bounding constraints. The synthesized IP is tested and the bounding constraints are iteratively modified until the characteristics of the synthesized IP are optimized/captured.

Abstract: In some embodiments, a system includes a memory device in a first clock domain region and a memory device and a digital signal processing (DSP) sub-system in a second clock domain region. In addition, a plurality of asynchronous first-in first-out (FIFO) data structures, each comprising a read interface, a write interface, and one or more data slots, store data generated from the DSP sub-system. The read interface operates in the first clock domain, and the write interface operates in the second clock domain.

Abstract: The present invention is directed to a configurable input/output interface and method for data transfer between a host and a target in a network environment. A method for providing data transfer between a host and a target in a network environment by a configurable input/output interface includes providing a logical identifier. The logical identifier is configurable for operation in at least two modes, the at least two modes including at least two of referencing multiple data transfer routes between the target and the input/output device utilizing a single logical identifier, referencing a single route between the target and the input/output device utilizing a logical identifier, and referencing a physical address of the target utilizing a logical identifier. Communications between the host and the target are managed by selecting a mode of the at least two modes operable by the input/output interface.

Abstract: A carbon nanotube memory cell for an integrated circuit wherein a chamber is constructed in a layer of a dielectric material such as silicon nitride down to a first electrical contact. This chamber is filled with polysilicon. A layer of a carbon nanotube mat or ribbon is formed over the silicon nitride layer and the chamber. A dielectric material, such as an oxide layer, is formed over the nanotube strips and patterned to form an upper chamber down to the ribbon layer to permit the ribbon to move into the upper chamber or into the lower chamber. The upper chamber is then filled with polysilicon. A silicon nitride layer is formed over the oxide layer and a contact opening is formed down to the ribbon and filled with tungsten that is then patterned to form metal lines. Any exposed silicon nitride is removed. A polysilicon layer is formed over the tungsten lines and anisotropically etched to remove polysilicon on the horizontal surfaces but leave polysilicon sidewall spacers.