Patents Assigned to LSI Logic
  • Method for combining states
    Patent number: 6948139
    Abstract: A method for combining states of a state machine employs manipulation of case statements in the RTL code implementing the state machine to allow selectable state combinations without duplication of code so that errors inherent in maintaining duplicate copies of the same RTL code may be eliminated.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventor: Richard L. Solomon
  • Intelligent engine for protection against injected crosstalk delay
    Patent number: 6948142
    Abstract: A method of protecting a net of an integrated circuit against injected crosstalk delay includes receiving a synthesized signal path structure and a value of maximum allowable injected crosstalk delay for a selected net in the signal path structure. The signal path structure is analyzed to calculate a skew correction and a net ramptime for the selected net. An injected crosstalk delay of the selected net is estimated from a net aggressor. A crosstalk protection scheme is selected for the selected net to minimize chip area of the integrated circuit while ensuring that the injected crosstalk delay of the selected net does not exceed the value of maximum allowable injected crosstalk delay.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Ruben Molina, Jr.
  • Measurement of package interconnect impedance using tester and supporting tester
    Patent number: 6946866
    Abstract: A tester head from a tester is used to mount a probe card. A DUT/load board has a socket which is configured to hold a substrate. Probe pins from the probe card make contact with bump pads on the substrate. Signal wires from the DUT/load board are fed to the tester, and the tester is connected to a DSO with a fast rise time signal head. During testing, a signal is launched using the DSO into a coaxial cable which is connected to the test head. The launched signal and the reflected signal are captured back by the DSO, and then fed into the tester. Using this data, post processing software is used to obtain the interconnect impedance versus time for the device (i.e., package) under test. The method and apparatus can be used in connection with both Flip Chip and Wire bonded products.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventors: Aritharan Thurairajaratnam, Mohan Nagar, Anand Govind, Farshad Ghahghahi
  • Multi-resolution Viterbi decoding technique
    Patent number: 6948114
    Abstract: A method for decoding an encoded signal. A first step generates a plurality of first precision state metrics for a decoder trellis in response to a plurality of first precision branch metrics. A second step generates a plurality of second precision state metrics for a selected subset of the first precision state metrics in response to a plurality of second precision branch metrics. A third step replaces the selected subset of first precision state metrics with the second precision state metrics. A fourth step stores the first precision state metrics and the second precision state metrics.
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: September 20, 2005
    Assignee: LSI Logic Corporation
    Inventors: Miodrag Potkonjak, Seapahn Megerian, Advait Mogre, Dusan Petranovic
  • Widely tunable ring oscillator utilizing active negative capacitance
    Patent number: 6943633
    Abstract: A ring oscillator that uses active negative capacitance at one or more stages of the ring oscillator to adjust the frequency of oscillation. By using a negative capacitance generator, negative capacitance may be placed in shunt with each stage of the ring, thereby reducing the effective input capacitance. Tuning of the ring oscillation frequency is accomplished without changing the bias point of each stage. The ring oscillation frequency may be increased, rather than reduced as in current approaches.
    Type: Grant
    Filed: September 2, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventor: Prashant Singh
  • Method and apparatus for mapping storage partitions of storage elements for host systems
    Patent number: 6944712
    Abstract: System and methods for managing requests of a host system to physical storage partitions. A storage system includes a plurality of storage elements with each storage element configured for providing data storage. A communications switch is communicatively connected to the storage elements for transferring requests to the physical storage partitions. A host system includes a storage router for mapping a portion of the physical storage partitions to logical storage partitions such that the host system can directly access the portion via the requests. Each of the storage elements includes a storage controller configured for processing the requests of the host system. The storage elements also include any of a disk storage device, tape storage device, CD storage device, and a computer memory storage device.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Bret S. Weber, Russell J. Henry
  • Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer
    Patent number: 6943055
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Data storage access through switched fabric
    Patent number: 6944152
    Abstract: A switched fabric, instead of a shared bus, establishes a data transfer path between a host device and a storage device. The host device accesses data stored on the storage device, but with data transfer speed and bandwidth advantages of a switched fabric architecture over a shared bus architecture. The components of a switch in the switched fabric are integrated together in a single integrated circuit, so as to have about the same size and cost as the prior art shared bus architecture. Additional storage devices and/or host devices may be connected to the switch and data transfer paths established between any host device and any storage device, but not between two storage devices. Another switch may be connected between host and storage devices to form redundant data transfer paths therebetween.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventor: Tom Heil
  • Architecture for mask programmable devices
    Patent number: 6943415
    Abstract: The present invention is directed to a semi-programmable ASIC using two metals for the metal layers. The semi-programmable ASIC may have a prefabricated first section and a customized second section. The prefabricated first section and the customized second section may each include one or more metal layers. The one or more metal layers included in the prefabricated first section may be used to define undifferentiated sets of electrical and logic elements. An undifferentiated set of electrical and logic elements may be a NAND logic gate, a NOR logic gate, or the like. The one or more metal layers included in the customized second section may be used to define logic functions of the undifferentiated sets of electrical and logic elements.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventor: Wilfred Corrigan
  • Via construction for structural support
    Patent number: 6943446
    Abstract: An integrated circuit having electrically conductive vias with a diameter of between about one micron and about fifty microns. Prior art vias have a diameter of between no less than 0.3 microns to no more than 0.8 microns. In this manner, stresses such as those that press down upon the top surface of the integrated circuit can be absorbed by the large vias and transferred past fragile layers, such as low k layers, so that the fragile layers are not damaged by the stresses.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: John P. McCormick, Ivor G. Barber, Kumar Nagarajan
  • Method of detecting spatially correlated variations in a parameter of an integrated circuit die
    Patent number: 6943042
    Abstract: A method of detecting spatially correlated variations that may be used for detecting statistical outliers in a production lot of integrated circuits to increase the average service life of the production lot includes measuring a selected parameter of each of a plurality of electronic circuits replicated on a common surface; calculating a difference between a value of the selected parameter at a target location and a value of the selected parameter an identical relative location with respect to the target location for each of the plurality of electronic circuits to generate a distribution of differences; calculating an absolute value of the distribution of differences; and calculating an average of the absolute value of the distribution of differences to generate a representative value for the residual for the identical relative location.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Robert Madge, Kevin Cota, Bruce Whitefield
  • Method of handling unreadable blocks during write of a RAID device
    Patent number: 6944791
    Abstract: Disclosed is a method for continuing a write operation in a RAID device when parity cannot be generated. In cases where a read error or plurality of read errors prohibits the proper calculation of parity for a block of data, the parity block may be written as a bad block of data for subsequent read operations. The parity block may be forced to be a bad block of data by writing a recognizable pattern of data with a known bad error correction code or other method of forcing a read error to occur on an otherwise good block of a disk storage device. This method allows the write operation to continue without halting the system as with conventional RAID devices.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: September 13, 2005
    Assignee: LSI Logic Corporation
    Inventors: Donald R. Humlicek, Charles E. Nichols, David Ulrich
  • User selectable editing protocol for fast flexible search engine
    Patent number: 6941314
    Abstract: A method of editing a sorted tree data structure includes selecting a minimum number of entries and a maximum number of entries in each vertex of the sorted tree data structure. If inserting an entry into a bottom vertex of the sorted tree data structure exceeds the maximum number of entries in the bottom vertex, then the entries are redistributed in the sorted tree data structure or a new bottom vertex is created so that no bottom vertex has more than the maximum number of entries and no fewer than the minimum number of entries. If deleting an entry from the bottom vertex results in fewer than the minimum number of entries, then the entries are redistributed in the sorted tree data structure or the bottom vertex is deleted so that no bottom vertex has fewer than the minimum number of entries and no bottom vertex has more than the maximum number of entries.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Ranko Scepanovic
  • Video decoding during I-frame decode at resolution change
    Patent number: 6940909
    Abstract: A method of buffering a video signal is disclosed. The method generally includes the steps of (A) storing a plurality of pictures decoded from the video signal having a first resolution in a memory space divided into a plurality of first buffers each having a first size, (B) dividing the memory space into a plurality of second buffers each having a second size in response to the pictures in the video signal changing to a second resolution, and (C) converting at least one unavailable buffer of the second buffers to an available condition by marking at least one unread picture of the pictures from the memory space as destroyed.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventor: Elliot N. Linzer
  • Bus interface system with two separate data transfer interfaces
    Patent number: 6941408
    Abstract: The present invention is directed to an interface. In an aspect of the present invention, an interface system suitable for coupling a bus interface controller with a back-end device includes a bus interface controller and a back-end device in which the back-end device is coupled to the bus interface controller via an interface. The interface includes a command queuing interface suitable for enqueueing a transaction, a command completion interface suitable for reporting transaction completion and a data transfer interface suitable for transferring data. The data transfer interface includes an inbound data transfer interface suitable for transferring data and an outbound data transfer interface suitable for transferring data. The inbound data transfer interface and the outbound data transfer interface are suitable for processing commands simultaneously.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventor: Richard L. Solomon
  • Built-in test for multiple memory circuits
    Patent number: 6941494
    Abstract: A memory test circuit includes a collar for coupling to a memory device for switching an address bus and a data bus of the memory device between an external circuit and the collar in response to a switching signal; and a controller coupled to the collar for generating the switching signal, a test vector, and control signals between the controller and the collar on as few as seven control lines for testing the memory device with the test vector. Multiple memory devices of various sizes may be tested with the same controller concurrently.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Alexander E. Andreev, Igor A. Vikhliantsev, Lav D. Ivanovic
  • Write compensation for a multi-level data storage system
    Patent number: 6940790
    Abstract: A system and method are disclosed for compensating during a data writing process for a transformation of input data by an optical disc data storage channel. A write strategy matrix is derived that maps a plurality of input sequences to a plurality of write strategy parameters. The input sequences each include a plurality of input data elements. When an input sequence is received, the write strategy matrix is used to determine in selected write strategy parameter that corresponds to the input sequence.
    Type: Grant
    Filed: February 2, 2000
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Judith C. Powelson, David K. Warland
  • Method for performing statistical post processing in semiconductor manufacturing using ID cells
    Patent number: 6939727
    Abstract: A method of manufacturing a semiconductor integrated circuit includes providing a fabricated integrated circuit on a wafer. A test fixture is connected to unencapsulated pads on the integrated circuit to monitor an operating parameter for the circuit and to determine a unique identifier for the die. The parameter is analyzed in post processing.
    Type: Grant
    Filed: November 3, 2003
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Ernest Allen, III, David Castaneda, Miaw Looi
  • Dielectric barrier films for use as copper barrier layers in semiconductor trench and via structures
    Patent number: 6939800
    Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventors: Hong-Qiang Lu, Peter A. Burke, Wilbur G. Catabay
  • Adaptive noise cancellation (ANC) for DVD systems
    Patent number: 6940982
    Abstract: An apparatus comprising an input, a noise cancellation circuit, an audio circuit and a mixing circuit. The input may be configured to receive one or more input signals. The noise cancellation circuit may be configured to generate a first processed audio signal having reduced noise in response to the input signals. The audio circuit may be configured to generate a second audio signal from a digital source. The mixing circuit may mix the processed audio signal and the second audio signals to generate an output signal.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 6, 2005
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins