Abstract: A method of synthesizing a clock tree for reducing peak power in an integrated circuit design includes partitioning a circuit design into a set of memory cells and a set of non-memory cells, partitioning the set of memory cells into segments, constructing a first clock tree having a first root vertex with a corresponding initial skew for each of the segments, constructing a second clock tree having a second root vertex with a corresponding initial skew for the set of non-memory cells, delay balancing the first root vertex and the second vertex clock tree, and inserting a clock buffer at a midpoint between the first root vertex and the second root vertex.

Abstract: A method and apparatus for traversing a queue of commands through part or all of the queue by selecting only the commands that need to be reissued. Commands to be reissued are labeled or designated as valid. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: A set of programming macros implement bit-fields in a variable, such as an unsigned integer structure having a bit-field definition number associated with each bit-field. The bit-field definition numbers have a value that defines the associated bit-field in terms of its end bits. In various embodiments, the macros extract the end bits from the value of the structure elements to form mask and shift values with which to manipulate the bit-fields.

Abstract: A method and apparatus for maintaining a fax transmission over a relay network that includes at least first and second portions and a relay portion that couples the first and second portions to each other. At a second gateway connecting the second portion to the relay portion, data frames received over the relay portion are processed to determine if they are corrupted, and signals are sent back to a first gateway to resend any data frames that are corrupted. The first gateway connects the first portion to the relay portion.

Abstract: A semiconductor memory device is provided as well as a method for operating the semiconductor memory device. The memory device includes a NOR array of memory cells and a NAND array of memory cells configured on the same monolithic semiconductor substrate. Each cell of the NOR array involves a single transistor, similar to each cell of the NAND array. The memory device is, therefore, an integrated circuit that includes not only the NOR and NAND arrays, but also the row and column decoders corresponding to each array. Furthermore, the integrated circuit includes the interface circuitry needed to transfer information as pages into and from the NAND array. The corresponding interface or controller is implemented on the same monolithic substrate as both the NAND array and the NOR array. Addresses targeted for the NOR array are sent as fully memory-mapped data into the NOR array, whereas addresses targeted for the NAND array are sent through the controller integrated within the semiconductor memory device.

Abstract: When a master device resets, flush commands are issued to a flush master register in the slave devices. A comparator compares the identification of the master device associated with the flush command to an identification of the master device associated with data for return by the slave device. A gate is responsive to the comparator to flush data from the data register that are pending for return.

Abstract: A semiconductor chip is provided which includes active and inactive IP cores. The spaces on the metal layer associated with the inactive IP cores includes voltage contrast inspection structures. The voltage contrast inspection structures serve to provide improved planarization of the metal layer and provided improved inspection capabilities.

Abstract: A battery charger system and method are disclosed for providing detailed battery status and charging method information and for controlling the charging of the battery. A controller is provided within the battery charger. The controller starts a measurement cycle. During the measurement cycle, current battery characteristics are determined by the battery charger. The controller determines a current charging method of the battery. Then controller then utilizes the battery characteristics and current charging method to determine an appropriate charging method for the battery. The controller then causes the battery charger to charge the battery utilizing the appropriate charging method.

Abstract: A method for planarizing a surface of an electrically conductive layer on a substrate, where the surface of the electrically conductive layer has relatively high features and relatively low features. A viscous material is applied to the surface of the electrically conductive layer, whereby at least the relatively low features are covered by the viscous material. The substrate is immersed in an electrically conductive solution. An electrical potential is applied between the electrically conductive layer and an electrode within the electrically conductive solution, whereby reaction kinetics favor erosion of the electrically conductive layer. The electrically conductive solution is agitated, thereby selectively uncovering the viscous material from at least features that are relatively high, and thereby preferentially planarizing at least the features that are relatively high.

Abstract: Methods and associated structure operable within a SCSI-based storage subsystem to adapt the storage controller for use with non-SCSI disk drives. A firmware layer of the present invention intercepts SCSI read/write requests and pass through command blocks (CDBs) generated by the storage management core of the controller and translates the requests and command structures into corresponding command structures for transmission to a non-SCSI disk drive. In like manner, the firmware layer of the present invention receives status information from non-SCSI disk drives and translates the status information into corresponding SCSI compatible status information. In one exemplary preferred embodiment, a storage subsystem designed for interaction with SCSI disk drives may be adapted in accordance with the present invention to utilize lower-cost, commodity disk drives such as IDE compatible disk drives.

Abstract: An adder based circuit embodied in an integrated circuit includes an input module, a carry module and an output module. The carry module has a minimum depth defined by a recursive expansion of at least one function associated with the carry module based on a variable k derived from a Fibonacci series. Invertor, XOR, XNOR (more preferably, OR(NOT(a),b)) and multiplexer elements are selectively coupled to the input and output modules to configure the adder based circuit as a subtractor, adder-subtractor, incrementor, decrementor, incrementer-decrementor or absolute value calculator. A computer process of designing the adder base circuit recursively expands the functions, and optimization of death, fanout and distribution of negations is performed.

Abstract: Local images of photolithographic masks are assigned to classes based on similarity of functions of circuits formed by the images, so that all of the images of a class can be corrected by correcting one of the members. Boundaries of photolithographic masks are corrected for diffusion of light by moving regions based on process light intensity and proximity of close connections. Boundaries are also corrected for shifting of photoactive material in photoresists by calculating the amount of shift based on light intensities at pattern points.

Abstract: An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Abstract: An integrated circuit is provided, which includes first, second and third power supply conductors. The second power supply conductor has a higher voltage than the first power supply conductor, and the third power supply conductor has a higher voltage than the second power supply conductor. A high voltage power supply decoupling capacitor is coupled between the first and third power supply conductors. A low voltage power supply decoupling capacitor coupled between the first and second power supply conductors. A voltage reducer is coupled between the second and third power supply conductors. A plurality of semiconductor devices is biased between the first and second power supply conductors.

Abstract: A method and apparatus for generating a delay in the timing of a bus or other logic circuit such that changes may be made to timing parameters without undue hardware design changes is disclosed. A counter is used to count a number of clock cycles to time the delay. The number of clock cycles is pre-loaded into the counter from a memory. This eliminates the need for costly hardware design changes when timing parameters change, since all that must be changed is the number of clock cycles to be counted, which can be modified by replacing or reprogramming the memory.

Abstract: Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs without impediment between the master device and its controller that have ownership of the bus, thereby conducting transactions via the peripheral bus and peripheral device. Communication with the master device and controller not having ownership is blocked, making the controller look busy to the master device and making the master device look idle to the controller. The ownership is assigned to the master/controller pairs using an arbiter arrangement.

Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate having an integrated circuit die attached thereto. The substrate includes at least one electrical ground plane and includes a plurality solder balls formed on a surface thereof. The solder balls include a set of “thermal” solder balls that are positioned near the perimeter of the package and electrically connected with a ground plane of the package. The IC die is electrically connected with the ground plane that is connected with the “thermal” solder balls. A heat spreader is mounted on the package with conductive mounting pegs that are electrically connected with the ground plane. The heat spreader is in thermal communication with the die and also in thermal communication with the set of “thermal” solder balls. This configuration enables a portion of the heat generated by the die to be dissipated from the die through the heat spreader into the set of “thermal” solder balls.

Abstract: The invention provides a method for OPC modeling. The procedure for tuning a model involves collecting cross-section images and critical dimension measurements through a matrix of focus and exposure settings. These images would then run through a pattern recognition system to capture top critical dimensions, bottom critical dimensions, resist loss, profile and the diffusion effects through focus and exposure.

Abstract: Methods and associated structure for mapping of data stripes and stripes in a RAID level 1E storage subsystem such that associated stripes of multiple physical stripes are physically contiguous. This mapping eliminates the need for duplicative reading (or writing) of stripes unrelated to the underlying I/O request performed to reduce the total number of I/O requests. This mapping also serves to limit the number of I/O requests required to read multiple stripes to the number of disk drives in the array and the number required to write multiple stripes and their corresponding mirrors to twice the number of disk drives in the array. The effects of this mapping therefore simplify RAID level 1E management in RAID controller with constrained memory and processing resources.

Abstract: A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.