Abstract: A method for compressing/decompressing data, comprising the steps of translating a first representation of data to a second representation of the data and translating the second representation of the data to a third representation of the data.

Abstract: Systems and methods for testing data lines to determine signal degradation in the data lines. A system includes a signal generator for generating a test pattern and for transferring the test pattern through the data lines. The system also includes an analyzer communicatively connected to the data lines to determine degradation of the test pattern in the data lines. The signal generator generates and transfers a first test pattern through the data lines. The first test pattern includes a first portion having a first polarity and a second portion having a second polarity. The signal generator then generates and transfers a second test pattern through the data lines in response to transferring the first test pattern. The test patterns may be repeated one or more times to determine cross talk caused by inductive coupling between data lines and additive reflections.

Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

Abstract: A method of routing a metal layer trace in an integrated circuit die includes steps of: (a) receiving as input a netlist of an integrated circuit die; (b) selecting a redistribution layer trace from the netlist for routing the redistribution layer trace between an I/O pad of the integrated circuit die and a termination point; (c) comparing a trace width of the redistribution layer trace with a maximum trace width limit; and (d) if the trace width of the redistribution layer trace exceeds the maximum trace width limit, then routing the redistribution layer trace as a plurality of separate parallel traces each having a trace width that is less than the selected maximum trace width limit.

Abstract: A device generally comprising a first circuit and a second circuit. The first circuit may be configured to (i) communicate with a host via a first bus (ii) using a small computer system interface (SCSI) protocol having a plurality of command descriptor blocks. The second circuit configured to (i) communicate with a remote device with a via a second bus, (ii) using an advanced technology attachment (ATA) protocol and (iii) translate a subset of the command descriptor blocks to the ATA protocol in application specific hardware.

Abstract: A system controls reproduction of a video transmission between a transmitter and a receiver. The system includes an encryptor with an offset generator adapted to receive the encrypted frame key and to generate a sequence of pseudo-random values for the color component; and an adder coupled to the offset generator and to the color component signal for providing an encoded color component signal. The system also includes a decryptor with a decryptor offset generator adapted to receive the encrypted frame key and to generate a decryptor pseudo-random value for the color component; and a subtractor coupled to the offset generator and to the color component signal for subtracting the offset signal from the color component signal.

Abstract: A system and method for implementing logic changes in integrated circuits (ICs). In a preferred embodiment, donor logic elements are taken from donator logic paths. The donated cells are implemented into a logic path altered by an ECO. The donated cell is replaced by spare cells. Timing analysis is done to ensure all logic paths are timing closed.

Abstract: A system for handling distributed results in a high-performance wide-issue superscalar processor having result-forwarding capability is disclosed. The system generally includes buffer logic configured to produce write data and write information to a register file. The register file generally has a plurality of registers and is adapted to receive the write information, the write data, and read information. The register file also includes logic configured to produce the write data as read data output when the read information and the write information specify the same register. An embodiment of the disclosed register file includes multiple registers for storing data, read logic, correction logic, and muxing logic.

Abstract: A method for creating a derivative semiconductor design layout is disclosed. The method generally comprises the steps of (A) receiving a plurality of changes from a user for a first layout of a semiconductor design having a plurality of first layers, (B) storing the changes in a plurality of second layers and (C) displaying the derivative semiconductor design layout to the user in response to logically operating on the first layers and the second layers.

Abstract: A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: A method and apparatus is provided for ensuring the integrity of data being transferred between two clock domains. Data is transferred on every clock signal from a faster clock domain to a slower clock domain. Data is collected by the data capture unit in two or more banks of registers for transfer to the second clock domain. The data collected has a first data size and is stacked with additional data of the first data size to generate data having a second data size. When two banks of registers are used, one bank of registers is being filled while the other bank of registers is passing data to the second clock domain. These two banks of registers provide two data paths to the synchronization logic for the second clock domain. This is especially advantageous when the limit of available bandwidth has been reached by one of the clock domains.

Abstract: A memory controller for aligning write data and a clock strobe signal provided to a memory device includes a delay line coupled to a local clock input and providing as an output a delayed local clock signal. A first latch circuit receives data to be written to the memory device as an input and has an output coupled to a data input of the memory device. The first latch circuit is clocked by a first one of the local clock signal and the delayed local clock signal and provides in response the write data to the data input of the memory device. A clock strobe generating circuit is clocked by a second one of the local clock signal and the delayed local clock signal. The clock strobe generating circuit has an output coupled to a clock strobe input of the memory device and provides the clock strobe signal to the memory device.

Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.

Abstract: A method and control system for controlling the delivery of a source chemical by a carrier gas. The carrier gas is delivered to a vessel containing the source chemical, and a flow of source chemical and carrier gas is carried from the vessel along a flow line. A sensor is used to detect light absorption of the flow, and the flow is adjusted based on what is detected. The sensor provides that light is directed transversely through the flow line and that the intensity of the light which passes through the flow line is detected by a detector. The detector forwards an output signal to a signal processing unit which thereafter adjusts the flow based on what was detected. The light may be filtered. The flow line includes at least a portion which provides an optical window for allowing light to pass therethrough.

Abstract: Methods and associated structure for improving storage system performance by reducing latency associated with communication medium transactions internal to a storage subsystem. In one aspect of the present invention, an I/O control element associated with a storage system transmits prefetch read requests to an associated storage element of the storage system in response to receipt of a host system request. This allows the storage element to commence data transfer to the I/O element in advance of the I/O element returning the data to the host system. Subsequent transfers of data from the storage element to the I/O element then overlap the transfer of data from the I/O element to the host.

Abstract: A configurable and scaleable multi-bus platform for developing, testing and/or debugging prototype systems to be implemented in an integrated circuit includes a backplane providing multiple busses. Multiple system bus cards can be coupled to the backplane, and each of the system bus cards includes a system bus which is electrically coupled to at least one bus on the backplane. The system bus cards also include a bus infrastructure device providing support logic for operating the system bus. Daughter cards, containing master or slave devices for particular design configurations, are coupleable to the system bus cards in order to simulate a system bus which will be implemented in the integrated circuit. The backplane and system bus cards, as well as other components, can be easily reused in other projects for designing, testing and debugging other integrated circuits.

Abstract: The present invention is directed to a converter device. In a first aspect of the present invention, a converter device includes a board having a first side and a second side. The first side includes a first set of contacts suitable for electrically contacting an integrated circuit having a first configuration. The second side includes a second set of contacts suitable for electrically contacting a circuit board having a second configuration. The second set of contacts is communicatively coupled to the first set of contacts.

Abstract: A high-bandwidth data transfer apparatus that is suitable for modular and scalable processing systems is disclosed. In one embodiment, the data transfer apparatus includes a local bus between each of several processing devices and associated memory modules. The local busses are each coupled to a cross-bus through a bus bridge that consists of multiplexers to steer address and data signals from a local bus along the cross-bus to another local bus. The multiplexer structure of the bridges allows the cross-bus to be dynamically divided into segments in any suitable manner to support multiple concurrent links over the cross-bus. A controller is provided to set the multiplexers in accordance with transfer requests that it receives from the various processing devices. The transfer requests may be of various types such as: single transfer, block transfer, and/or message transfer. The controller may include a request queue for each type of transfer request.

Abstract: The digital programmable delay scheme with automatic calibration is an alternative to PLLs, DLLs, fixed delay cells and other methods of delay. The method and circuit sets a delay in a programmable delay cell in an oscillator circuit and uses a reference clock to calibrate the oscillator clock frequency. The programmable delay, once set, may then be used to determine a desired delay for a signal that passes through the programmable delay cell as well as another portion of the oscillator circuit. The circuit preferably uses two counters that are controlled by calibration and control logic in which one counter is clocked by the reference clock and the other is clocked by the oscillator circuit clock. After a predetermined time, the calibration and control logic compares the two count values and determines if the programmable delay cell of the oscillator circuit needs to be adjusted.