Abstract: On-chip absolute value measurement circuit and an on-chip capacitor mismatch value measurement circuits are provided. The absolute value measurement circuit begins charging a capacitor. When the voltage across the capacitor reaches a first threshold, the absolute value measurement circuit starts a counter. When the voltage across the capacitor reaches a second threshold, the counter stops. The counter value is provided as digital output. A computer device reads the digital output and calculates the absolute value of the capacitor based on the counter value. The mismatch measurement circuit repeatedly charges an evaluation capacitor and transfers the charge from the evaluation capacitor to an integrating capacitor. For each transfer of charge, a counter is incremented until the voltage across the integrating capacitor reaches a threshold voltage. The counter value is provided as digital output. This process is repeated for each evaluation capacitor on the chip.

Abstract: A method and system for performing optical proximity correction (OPC) on an integrated circuit (IC) chip design is disclosed. The system and method of the present invention includes exploding calls on an element list to generate an expanded element list, defining a local cover area for each call on the expanded element list, classifying congruent local cover areas into corresponding groups, and performing an OPC procedure for one local cover area in each group By defining the local cover area for each call and grouping congruent local cover areas, only one OPC procedure (e.g., evaluation and correction) needs to be performed per group of congruent local cover areas. The amount of data to be evaluated and the number of corrections performed is greatly reduced because OPC is not performed on repetitive portions of the IC chip design, thereby resulting in significant savings in computing resources and time.

Abstract: Disclosed is a method for converting a SPICE format circuit description to a standard cell HDL netlist, such as Verilog, allowing simulation and verification in HDL format. SPICE elements may be converted to circuit functions and corresponding standard cells are then selected. The SPICE netlist is employed to define timing paths. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of the SPICE simulation. The present invention may also employ SPICE to Verilog conversion wherein a SPICE netlist is converted to a Verilog standard cell netlist. Timing information from SPICE simulation is correlated with timing characteristics of the standard cells in the Verilog netlist and a standard delay file is produced such that, when applied to the standard cells, timing approximates that of SPICE simulations.

Abstract: A BISR scheme which provides that fuse blocks are shared between memories to reduce hard-BISR implementation costs. The scheme includes a plurality of memories serially connected to a fuse controller. A plurality of fuse blocks are also serially connected to the fuse controller. There are more memory instances than there are fuse blocks, and the fuse controller is configured to allow the fuse blocks to be shared between memories. Preferably, each fuse block includes fuse elements which can be programmed with the memory instance number which needs to be repaired. The fuse block reduces routing congestion and is preferably configured to provide the flexibility of assigning any fuse block to any instance that needs repair. The programmable fuse elements are preferably loaded into a counter (which is preferably part of the fuse controller) which ensures that the correct block information gets loaded into the corresponding memory instance.

Abstract: A BGA package having a multiplicity of power segments configured for power connection to integrated circuit die is disclosed. The BGA package substrate includes an integrated circuit die and a ground ring. The substrate also includes a first power ring with a plurality of spaced apart first power ring segments arranged around the die. A second power ring having a plurality of spaced apart conductive second ring segments is also formed around the die. A plurality of vias that penetrate through the substrate are provided to accommodate electrical connections to the segments of the first and second power rings and to the ground ring. The package includes bonding wires for connecting the die to the first and second ring segments and ground ring. Additionally, the package is commonly encapsulated to protect the die and wires.

Abstract: A system and method are presented for neutralizing the electric charge binding a semiconductor wafer to an electrostatic chuck. When processing of a semiconductor wafer has been completed, lifter pins, driven by solenoids or pistons, are provided within the chuck to remove the wafer. However, if the electrostatic force has not been completely dissipated, the pins may have to push very hard against the wafer to dislodge it. When this occurs, the wafer may be violently displaced from the chuck, resulting in misplacement of the wafer, or even damage. A system and method are disclosed herein for completely neutralizing the electrostatic charge before removal of the wafer is attempted. Neutralization is detected as the point at which the electrostatic force opposing the lifting mechanism reaches a minimum.

Abstract: A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600° C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

Abstract: A method of increasing computer system bandwidth for computer system having two or more memory complexes is disclosed in which exclusive OR operations are performed on the data from the data regions to generate parity information which is stored in the same single cache pool as the data regions. By using a single cache pool for related data regions, bandwidth and performance are improved.

Abstract: A method for designing and using a partially manufactured semiconductor product is disclosed. The partially manufactured semiconductor product, referred to as a slice, contains a fabric of configurable transistors and at least an area of embedded memory. The method contemplates that a range of processors, processing elements, processing circuits exists which might be manufactured as a hardmacs or configured from the transistor fabric of the slice. The method then evaluates all the memory requirements of all the processors in the range to create a memory superset to be embedded into the slice. The memory superset can then be mapped and routed to a particular memory for one of the processors within the range; ports can be mapped and routed to access the selected portions of the memory superset. If any memory is not used, then it and/or its adjoining transistor fabric can become a landing zone for other functions or registers or memories.

Abstract: A carrier substrate includes an access region placed within the interior of the substrate that facilitates backside access to an integrated circuit die without damaging electrical integrity of the carrier substrate, a ring of die connection pads placed around the access region, and an array of package connection pads positioned around the perimeter of the top surface of the carrier substrate. In one embodiment, the perimeter depth of the array of package connections pads is selected to correspond to the number of electrical traces routable between minimally spaced package connection pads. The basic carrier substrate design is used to create an integrated circuit carrier family with each particular circuit carrier configured to receive a range of integrated circuit sizes and I/O counts such that each circuit carrier overlaps in size range with at least one other circuit carrier.

Abstract: A package shell that is electrically and thermally conductive is placed over an integrated circuit die and associated wire-bond connections to electromagnetically shield the resulting integrated circuit package. The package shell is attached to the top surface of a substrate bearing the integrated circuit die and is electrically connected to a grounding path. The package shell may be filled with a thermally conductive filler in order to increase the heat dissipation and EMI shielding of the resulting integrated circuit package.

Abstract: An inventive semiconductor chip is provided. Generally, shallow trenches containing field oxide are provided on a substrate. At least one semiconductor device is formed between the shallow trenches. An oxide layer is formed over the at least one semiconductor device and the field oxide. An etch stop layer is formed over the oxide layer. An inter layer dielectric layer is formed over the etch stop layer. At least one contact hole is etched through the inter layer dielectric layer, the etch stop layer and at least partially through the oxide layer. The contact hole is filled with a conductive material.

Abstract: A method and system for testing an integrated circuit package is disclosed. The integrated circuit package includes a plurality of daisy chain loops that are connected to a pair of package pads, wherein adjacent daisy chain loops are oppositely biased. Aspects of the present invention include forming a first plurality of gangs of electrically coupled daisy chain loops having a first bias and forming a second plurality of gangs of electrically coupled daisy chain loops having a second bias. Each one of the first plurality of gangs is individually coupled to an electrical measurement device, while the second plurality of gangs are electrically coupled in common, and the common gang is coupled to the electrical measurement device.

Abstract: A method of forming a metallization interconnection system within a via. A first liner layer of titanium is deposited to a first thickness in the following manner. A substrate containing the via is placed within an ion metal plasma deposition chamber that contains a titanium target. The ion metal plasma deposition chamber is evacuated to a first base pressure. A first flow of argon is introduced to the ion metal plasma deposition chamber at a first deposition pressure. The substrate is biased to a first voltage. A plasma within the ion metal plasma deposition chamber is energized at a first power for a first length of time. A second liner layer of TixNy is deposited to a second thickness on top of the first liner layer of titanium in the following manner. A first flow of nitrogen and a second flow of argon are introduced to the ion metal plasma deposition chamber at a second deposition pressure. The substrate is biased to a second voltage.

Abstract: An apparatus and method for sharing a boot volume among server blades. The shared boot volume may be a single drive or a RAID volume. The shared boot volume is first partitioned into boot slices. Next, individual boot slices of the shared boot volume are correlated with individual server blades, which share the shared boot volume. When a boot slice is correlated with a server blade, the boot slice is presented to the server blade, and the server blade sees the boot slice and only the boot slice, and owns the boot slice. This correlation is transparent to the OS or applications on a given server blade, because the I/O controller masks all boot slices but the one owned by that server blade. As far as OS and applications are concerned, the server blade just has a single boot slice as a dedicated local drive.

Abstract: Systems and methods for analyzing data transferred through an SPI data bus are presented. In one exemplary preferred embodiment of the invention, an SPI data probe imitates an SPI device coupled to the SPI data bus and receives data from the SPI data bus so that the data may be analyzed. The SPI data probe transfers the data to an analysis unit without substantially altering impedance more than the SPI device would. The SPI data probe includes connectors configured for coupling the probe to the SPI data bus and for coupling the probe to an analysis unit. The SPI data probe also includes circuitry that may buffer, compensate and deskew the data as an SPI device would.

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: In a storage area network having a host device and a consolidated storage array (CSA), one of the storage arrays of the CSA acts as a primary device of the CSA to form logical data volumes across one or more of the total storage arrays of the CSA. The logical data volumes typically have performance requirements that cannot be met by a single storage array. Upon receipt of a command from the host device to create one of the logical data volumes, the CSA primary device analyzes the storage arrays to determine a combination thereof, across which the logical data volume will be striped, that best satisfies the performance requirements. The CSA primary device configures these storage arrays to form the logical data volume and sends striping information, which defines the logical data volume, to the host device. Striping software based on the host device responds to the striping information to access the logical data volume.

Abstract: A dual exposure source lithography system forms a first and a second portion of a pattern on a wafer. An optical lithography module forms the first portion of the pattern. A non-optical lithography module forms the second portion of the pattern using a non-optical lithography exposure source. The non-optical exposure source is an electron beam lithography source, an EUV source, an x-ray source, or another next generation lithography system exposure source. A mask design file is decomposed into separate design files reflecting critical and non-critical components of the pattern to be formed on the wafer.

Abstract: A circuit generally comprising a memory element and a controller. The memory element may define a semaphore allocatable to a resource. The controller may be configured to (i) present a granted status in response to a processor reading a first address while the semaphore has a free status, (ii) set the semaphore to a busy status in response to presenting the granted status, and (iii) present the busy status in response to the processor reading the first address while the semaphore has the busy status.