Abstract: A method and apparatus are provided for detecting contact between a wafer blade of a wafer-handling robot and a component in a wafer-handling system. The robot moves the wafer blade within the system while the wafer blade is maintained at an electrical potential, which is different from an electrical potential of the component. Contact between the wafer blade and the component is detected by sensing a change in the electrical potential of the wafer blade during the contact.

Abstract: In a system having multiple master devices coupled to a shared resource, methods and structure for a state machine based memory model associated with each bank of memory to provide an arbiter with information for generating optimal sequences of memory commands to enable improved memory subsystem bandwidth utilization. The memory model corresponding to each bank of memory emulates the latencies involved with switching of active rows or pages in the corresponding bank. Signals generated by the memory model are applied to the arbiter to enable the arbiter to efficiently determine the optimal timing for generation of memory access commands corresponding to that bank.

Abstract: The present invention is directed to a system and method for increased data availability. In an aspect of the present invention, a method includes receiving a SMART indication from a data storage device included in a plurality of data storage devices configured as a RAID array. Data from the data storage device which originated the SMART indication is replicated to a second data storage device. The second data storage device was not originally configured in the RAID array with the plurality of data storage devices for data storage. The data storage device which originated the SMART indication from the RAID array is removed, thereby resulting the second data storage device and the plurality of data storage devices configured as a RAID array.

Abstract: The present invention is a method, system, and product for testing operating characteristics of a continuous-time or discrete-time device under test, which is included within a circuit. The operating characteristics of the continuous-time or discrete-time device are tested utilizing electronic components that already exist within the circuit such that a test circuit is not utilized to test the device. The circuit includes a variable gain amplifier and an automatic gain correction (AGC) circuit. The operating characteristics of the device are tested utilizing the variable gain amplifier and said AGC circuit.

Abstract: The present invention discloses a system and method for optimizing remote data distribution. A system and method for optimizing remote data includes receiving a request for content at a first storage device. The first storage device may include a map which may be analyzed to determine if a copy associated with the content request is present at the first storage device. The map may include at least one map entry having an identifier suitable for describing a range of addressable data blocks. If a copy associated with the content request is initially present, the copy may be provided to a user that requested the content. If the requested content is not initially present, a copy of the content may be retrieved by the first storage device from a second storage device. After receipt of the copy, a map located at the first storage device may be updated to reflect storage of the copy of requested content at the first storage device.

Abstract: A semiconductor substrate having high density signal routing is provided. The semiconductor substrate may include first signal traces electrically connected to a first row of signal bonding pads and routed on a first layer of the substrate. In addition, the substrate may include second signal traces electrically connected to a second row of signal bonding pads and routed on a second layer of the substrate. The first layer may be arranged in a strip line configuration, and the second layer may be arranged in a micro strip line configuration. Alternatively, the second signal traces may be arranged in a strip line configuration. In an embodiment, the first and second signal traces may be routed as differential pairs with approximately equal trace lengths. In another embodiment, all of the first and second signal traces may be routed as differential pairs.

Abstract: A probe structure for testing impedance of a package substrate using time domain reflectometry. A connector electrically connects the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. An electrically conductive cantilever signal pin is electrically connected to the signal conductor. The electrically conductive cantilever signal pin has a tip for making an electrical connection with an electrically conductive structure to be tested on the package substrate. The electrically conductive cantilever signal pin is electrically isolated by and sheathed within a ground shield that is electrically connected to at least one of the ground conductor and electrically conductive cantilever ground pins. The electrically conductive cantilever ground pins are electrically connected to the ground conductor.

Abstract: A mechanism is provided for controlling the heat output of a controller by monitoring the temperature of the controller using an embedded heat sensor. The IO processor monitors the temperature and controls the rate of the IO flow to control the temperature. The IO processor accomplishes this by checking the current temperature every time it gets a timer interrupt. If the temperature becomes too high, the IO processor may slow down the processor speeds in the controller. The IO processor may also slow down the throughput by inserting a delay between each IO request processed. Furthermore, the IO processor may slow down the rate at which data is passed onto the bus. Still further, the IO processor may insert a delay between batches of IO requests. By slowing down the IO flow, the IO processor decreases the overall power consumption and, thus, controls the heat output.

Abstract: Within metal interconnect layers above a substrate of an integrated circuit, a vertical metal-insulator-metal (VMIM) capacitor is formed by the same damascene metallization types of processes that formed the metal interconnect layers. The metal interconnect layers have horizontal metal conductor lines, are vertically separated from other metal interconnect layers by an interlayer dielectric (ILD) layer, and electrically connect to the other metal interconnect layers through via connections extending through the ILD layer. One vertical capacitor plate of the VMIM capacitor is defined by a metal conductor line and a via connection. The other vertical capacitor plate is defined by a metal region adjacent to the metal conductor line and the via connection. The metal conductor line, the via connection and the metal region are formed by the damascene metallization processes.

Abstract: Disclosed is a method for automatically testing the deskew setting for the clock in a parallel data interface. The deskew value is varied to a high and a low limit to the point where errors occur when transmissions occur. After determining the high and low operable limits of the deskew values, an optimum deskew setting may be determined and set for the system. The present invention may be used as a design verification technique, for optimizing a system after integration, or for further optimization of the deskew value after performing a training pattern for optimizing transmission performance.

Abstract: An integrated circuit package comprises a cavity for housing an integrated circuit (IC) and an antenna provided as part of the package that is located substantially outside the cavity. The antenna may be located on the floor of the IC package that lies in the region outside of the IC cavity. Alternatively, the antenna may be located on the upper or lower surface of the lid sealing the IC package. The antenna may be placed in the floor or on a surface of the IC lid by forming depressions in the floor or lid surface and depositing conductive material in the depressions. The conductive material deposition may be by sputtering, evaporation, or other known physical or chemical deposition method. Antennas formed in the upper surface of an IC lid may be coupled to a pin of the IC package so that the antenna may be electrically coupled to a transceiver component on the IC within the package.

Abstract: A switched architecture for dual, independent storage controllers overcomes latency and coherency problems by an inter-controller command interchange scheme. The switched architecture permits a read or write command to be presented to either storage controller to effect data transfer on the same or the other storage controller. Communication between the two storage controllers is effected through internal Infiniband switches.

Abstract: A method of testing a core module includes steps of: (a) providing a core module of an integrated circuit design; (b) connecting an end user input and a core module test input to separate I/O pins of the core module to isolate logic associated with an end user signal from that associated with a core module test signal; and (c) multiplexing the end user signal and the core module test signal in the core module in response to a core module test mode signal.

Abstract: An instruction pipeline for a DSP with fusing logic for combining multiple instructions into a single control word which can be executed by one execution unit. The pipeline fetches a greater number of instructions than the number of execution units to which it can issue instructions. It applies grouping rules to the instructions and also identifies pairs, or larger groups, of instructions which can be combined, or fused, into a single control word which can be executed by one execution unit. Issuance of a fused control word to a single execution unit effectively allows two or more instructions to be executed simultaneously in one execution unit.

Abstract: The present invention is directed to a system and method for coevolutionary circuit design. A system suitable for providing integrated circuit design may include a memory suitable for storing a first set of instructions and a second set of instructions and a processor communicatively coupled to the memory. The processor is suitable for performing the first set of instructions and the second set of instructions. The first set of instructions is suitable for configuring a processor to provide an integrated circuit development environment in which a support methodology for an integrated circuit is created. The second set of instructions is suitable for configuring a processor to provide tools for implementing a platform architecture of an integrated circuit in which the platform architecture supplies a structure of the integrated circuit.

Abstract: Objects are placed in a rectangle and their coordinates of the objects and are adjusted to establish a substantially uniform density of objects in the rectangle. The evaluation of coordinates is performed by placing the wires between cells coordinates and adjusting the cell coordinates to connect the cells to the wires. The substantially uniform density is achieved by dividing the rectangle into first and second rectangles having equal free areas and into third and fourth rectangles having equal areas of objects. The coordinates of the objects are adjusted based on boundaries between the first and second rectangles and between the third and fourth rectangles.

Abstract: Methods and associated structure operable within a SCSI-based storage subsystem are provided to adapt the storage controller for use with non-SCSI storage enclosures. A firmware layer of the present invention intercepts SCSI read/write requests and pass-through command blocks (CDBs) generated by the storage management core of the controller and translates the requests and command structures into corresponding command structures for transmission to a non-SCSI storage enclosure. In like manner, the firmware layer of the present invention receives status information from non-SCSI storage enclosures and translates the status information into corresponding SCSI compatible status information. In one exemplary preferred embodiment, a storage subsystem designed for interaction with SCSI storage enclosures may be adapted in accordance with the present invention to utilize lower-cost, IDE compatible storage enclosures.

Abstract: A copper interconnect with a Sn coating is formed in a damascene structure by forming a trench in a dielectric layer. The trench is formed by electroplating copper simultaneously with a metal dopant to form a doped copper layer. The top level of the doped copper layer is reduced to form a planarized surface level with the surface of the first dielectric layer. The doped copper is annealed to drive the metal dopants to form a metal dopant capping coating at the planarized top surface of the doped copper layer.

Abstract: A circuit isolation technique that uses implanted ions in embedded portions of a wafer substrate to lower the resistance of the substrate under circuits formed on the wafer or portions of circuits formed on the wafer to prevent the flow of injected currents across the substrate. The embedded ions provide low resistance regions that allow injected currents from a circuit to flow directly to a ground potential in the same circuit rather than flowing across the substrate to other circuits. High energy implantation processes on the order of 1 MeV to 3 MeVs can be used to implant the ions in embedded regions. Multiple energy levels can be used to provide thick embedded layers either prior to or after application of an epitaxial layer. Various masking materials can be used to mask the isolation regions during the implantation process, including hard masking materials such as silicon dioxide or silicon nitride, poly-silicon or an amorphous silicon layer, and a photoresist layer.

Abstract: A method and apparatus for initializing an optical recording medium comprising a phase change material using a series of flashes of light. A series of low-power, high duty cycle flashes of light are produced to initialize the media to a crystalline form, onto which data may be recorded. In accordance with another aspect of this invention, a spiral flash bulb with centrally located connectors comprises the flash illumination source for initializing the optical recording media.