Abstract: A phase-locked loop within an integrated circuit assembly is provided. The phase-locked loop includes a plurality of subcells of semiconductor devices arranged in a base layer pattern on base layers of the integrated circuit assembly. One or more metal layers are formed over and interconnect the plurality of semiconductor devices in a metallization pattern. The phase-locked loop has an output frequency range that is changeable with a change to the metallization pattern without a corresponding change to the base layer pattern.

Abstract: Integrated circuits are designed having optimal signal timing between and among cells. A set of identities are generated corresponding to logic operations and to library cells in technology basis. A resynthesis window is created for the identities having less than a predetermined depth of critical variables. Logic equations of the resynthesis window are transformed using the identities, and the resynthesized window area is optimized.

Abstract: Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are then formed at least one of above and adjacent to the metal line formed on the integrated circuit substrate such that the density of metal on the integrated circuit substrate is greater than a specified density, thereby ensuring that a surface of dielectric formed above the metal line remains substantially planar after application of CMP to the dielectric layer.

Abstract: An integrated circuit having signal traces, power traces, and ground traces. The signal traces are disposed on at least one signal distribution layer, and the signal traces on the at least one signal distribution layer are formed at no more than a first thickness. The power traces and ground traces are formed on at least one power ground distribution layer, where the at least one power ground distribution layer is an overlying layer of the integrated circuit relative to the at least one signal distribution layer. The power traces and ground traces on the at least one power ground distribution layer are formed at no less than a second thickness that is greater than the first thickness of the signal traces. In this manner, the signal traces, which can be formed with a relatively thin thickness, can be placed very close together on the signal distribution layers, and have sufficient conductivity for the signals transmitted thereon.

Abstract: Methods and associated structure for providing a substitute, predetermined, fixed length when transferring burst transactions from one device to another through a bridge device where the burst transaction has an indefinite length specified. In one exemplary preferred embodiment, an AMBA AHB bus bridge slave device recognizes initiation of burst transactions of a indefinite length and translates the indefinite length burst transactions on the first bus into appropriate bus transactions for application to a second bus or device having a predetermined fixed length for the transferred the burst transactions. In a second embodiment, a slave device acting as a bridge receives a burst of indefinite length and translates the bus request into one with a predetermined fixed length for application to a device controller.

Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.

Abstract: A method and system is provided for automatically calibrating a masking process simulator using a calibration mask and process parameters to produce a calibration pattern on a wafer. A digital image is created of the calibration pattern, and the edges of the pattern are detected. Data defining the calibration mask and at least one of the process parameters are input to a process simulator to produce an alim image estimating the calibration pattern that would be produced by the masking process. The alim image and the detected edges of the digital image are then overlaid, and a distance between contours of the pattern in the alim image and the detected edges is measured. One or more mathematical algorithms are used to iteratively change the values of the processing parameters until a set of processing parameter values are found that produces a minimum distance between the contours of the pattern in the alim image and the detected edges.

Abstract: Methods and associated structure for booting host adapter devices in a system where the host adapter devices are devoid of independent, nonvolatile memory devices for storage of programmed instructions operable within the intelligent host adapter device. The operational programmed instructions for the intelligent host adapter device are stored in the nonvolatile memory of the system motherboard along with the standard BIOS code of the system. The intelligent host adapter device operational programmed instructions are then downloaded by the BIOS code into the host adapter's volatile local program memory to initialize operation of the intelligent host adapter device. Further, device driver code operable in the operating system on the motherboard will upload the previously downloaded programmed instructions from the intelligent host adapter so that the programmed instructions may be reloaded to the host adapter in response to reset conditions, power management events, and other conditions.

Abstract: The present invention is directed to a system and method of finding Boolean symmetries. In aspects of the present invention, a method, system and computer-readable medium constructs a symmetry tree for any Boolean function. A data structure which describes groups of commutative variables of a Boolean function is called a symmetry tree of the Boolean function.

Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.

Abstract: A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input data stream into a plurality of split signals each at a frequency of the desired output frequency. A plurality of catchers identify valid bits of each respective split signal. A shifter shifts valid bits identified by at least some of the catchers by a predetermined number which establishes a de-serialization level for frequency reduction or phase shifting. An output provide an output data stream at the desired output frequency.

Abstract: A mask for use in a photolithographic process. The mask includes a plate or substrate having first and second opposite surfaces, a first image on the first surface of the substrate and a second image on the second surface of the substrate. When the mask is used in a photolithographic process, energy is reflected by the first image prior to entering the substrate and energy is reflected by the second image after passing through the substrate.

Abstract: An attenuated phase shift mask is formed using a non-linear optical material for both fiducial features and pattern features. The non-linear optical material selected has predetermined transmission at the actinic exposure wavelength and a smaller transmission at the fiducial recognition wavelengths.

Abstract: A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.

Abstract: An amplifier for a differential signal drain is able to amplify a signal over a frequency range and boost the signal within a specified frequency range. A resistor is placed between the drain and gate of the first transistor of a cascode amplifier and can be selected to provide additional signal boost at a specified input frequency. An additional input transistor may be added to provide a stepped amplification over the frequency range. The amplifier is further able to reject common mode signals by using regulating transistors.

Abstract: A method for reducing latency in conversions from a SMII (Serial Media Independent Interface) to a MII (Media Independent Interface). The method involves generating receive and transmit clock signals from a physical layer device; generating receive and transmit clock signals at a media access controller; and synchronizing the clock signals at the media access controller and the clock signals at the physical layer device such that MII clocks are generated from the SMII and a synchronization signal of the SMII is always delayed 8 nsec from a positive edge of the MII clock.

Abstract: A system and method to establish an end-to-end error correcting protocol between two voice band data modems over a network including voice band data relay gateways, where part of the end-to-end connection is via low data rate narrowband network. Using a partial implementation of V.42 LAPM protocol within the data relay gateways, the system allows the independent selection of modulation schemes at each gateway as well as increased user data throughput by removing non-informational data. Flow control of the user data to match the channel rate of the narrowband network may also be provided.

Abstract: A method of representing a net includes steps of: (a) receiving as input vertices of a net in an integrated circuit die; (b) calculating rounded coordinates having a selected resolution for each of the vertices; (c) calculating rounded coordinates having the selected resolution along the net between each of the vertices; and (d) generating as output the rounded coordinates to represent the net.

Abstract: A pre-diffused high density array of core memory cells is provided in a metal programmable device. The peripheral logic is made up of gate array cells in the metal programmable device. The peripheral logic may be configured to access the core memory cells as various memory types, widths, depths, and other configurations. If the entire memory is not needed, then the unused memory cells can be used as logic gates. The application-specific circuit, including peripheral logic, memory interface logic, and memory configuration is programmed with a metal layer.

Abstract: The present invention a system and method are provided for performing an inter-frequency search with reduced loss of link frames in a CDMA system. The CDMA system includes a base station (20) and a mobile station (50). The mobile station (50) has a searcher (164), which searches for pilot channels. The signal strengths of these pilot channels are then reported to the base station (20). This searching results in erased portions of a data frame (238). After the signal strengths are reported to the base station (20), the mobile station (50) informs the base station (20) of the parameters related to the search. These parameters may include the frame of the search, the start position of the search, and the length of the search. The mobile station (50) and the base station (20) then replaces the erased portions of the frame with corrective data such as soft zeros.