Abstract: A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the IDDQ test limit based upon the measured IDDQ value. In some embodiments, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure IDDQ value to an IDDQ test limit of an integrated circuit. In some cases, the means for determining the IDDQ test limit may further include a means for increasing a substrate leakage current of the test structure.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or cone of logic cells which cause the desired output signal at a selected output signal transition time.

Abstract: An integrated circuit device (10) comprises a semiconductor die (14) and an optical signal emitting diode (18) for communicating an optical signal, such as a clock or trigger signal, to individual circuits on the die (14). Each circuit includes a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material (20) encapsulates the emitter diode (18) and the die (14). The optically communicated signal has very low skew, which is independent of the topology of the die (14).

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.

Abstract: A data transmission buffer circuit is provided for buffering communication data, which is divided into a plurality of multiple-bit data frames that have a start and an end. The buffer circuit includes a first-in-first-out (FIFO) buffer and a frame counter. The FIFO buffer has a write port and a read port. The write port includes a data input, a write control input and an end-of-frame flag input, which indicates whether data on the data input includes the end of one of the data frames. The read port includes a data output, a read control input, and an end-of-frame flag output, which indicates whether data on the data output includes the end of one of the data frames. The frame counter is coupled to the write port and the read port and generates a frame count output that represents a number of the data frames stored in the FIFO buffer.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical.

Abstract: In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

Abstract: An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.

Abstract: Methods and associated structure for on the fly (dynamic) transition between versions among a management application process and an associated I/O subsystem. A management application program operable on a management system coupled to the I/O subsystem instantiates a script engine to execute script language commands for communicating with the I/O subsystem on behalf of the management application. The particular script engine instantiated is one that is compatible with the present revision of firmware operable in the I/O subsystem. When a script command execution causes a firmware upgrade in the I/O subsystem, the present script engine saves its state of operation, notifies the management application of the upgrade and resultant incompatibility and terminates. The management application then instantiates a new script engine compatible with the newly upgraded firmware version in the I/O subsystem.

Abstract: A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and shared memory. Bus snooping capabilities are enabled by a stand-alone bus snooping device connected to the bus and the caching device or by bus snooping functions incorporated into the caching device. The bus snooping device monitors communications on the bus and causes invalidation of cached information to maintain cache coherency before the communications complete.

Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

Abstract: A modem generally comprising an analog front end circuit, a hybrid circuit, and a variable impedance element. The hybrid circuit may be configured to couple the analog front end circuit to a transmission line. The variable impedance may be disposed within the analog front end circuit and connected to the hybrid circuit to trim an echo cancelling function of the hybrid circuit.

Abstract: An apparatus and method for protecting a probe card during a sort sequence are provided. With the apparatus and method, one or more probe card protectors are attached to a probe card. When the wafer is driven toward the probe card, if an amount of overdriving of the probe card occurs, the probe card protectors come into contact with the wafer. By pressing against the wafer, the probe card protectors generate a force that causes a driver motor of the driving mechanism to stall, thereby avoiding any further overdrive of the probe card and avoiding damage to the probe card.

Abstract: An integrated circuit having circuit structures, including at least one of logic elements and memory elements. A core is disposed at an interior portion of the integrated circuit. The core contains core power contacts and core ground contacts for providing electrical power to the circuit structures during functional operation of the integrated circuit. A peripheral is disposed at an edge portion of the integrated circuit. The peripheral contains signal contacts for sending and receiving electrical signals between the circuit structures and external circuitry. The peripheral also has peripheral power contacts and peripheral ground contacts for providing electrical power to the circuit structures during testing of the integrated circuit. The peripheral power contacts are redundant to at least some of the core power contacts, and the peripheral ground contacts are redundant to at least some of the core power contacts.

Abstract: A method for generating constraint codes in a stream of data having a plurality of multi-bit source words, comprising the steps of (A) checking a sequence portion of the multi-bit source words for one or more constraint violations and (B) if no constraint violations are detected, modifying a predetermined portion of each of the multi-bit source words to generate a plurality of corresponding multi-bit code words configured to prevent the constraint violations of the sequence portions across an adjacent two of the multi-bit code words.

Abstract: A signal amplitude comparator which includes a first differential input circuit that is biased, is configured to receive an input voltage and is configured to generate a first output current that is a non-linear function of the input voltage, a second differential input circuit which is biased similarly to the first differential input circuit, is configured to receive a reference input voltage and is configured to generate a second output current that generally tracks process, temperature and supply variation, and a comparator which is connected to the first differential input circuit and the second differential input circuit and is configured to receive the first output current from the first differential input circuit and the second output current from the second differential input circuit. The comparator is configured to compare the first and second output currents and generate an output which indicates whether the input voltage exceeds a pre-determined threshold value.

Abstract: A clock divider circuit and methods of operating same includes a standard integral clock divider circuit and a phase slip non-integral divider circuit for high granularity non-integral clock division. A multi-phase frequency synthesizer produces a plurality of phases of a clock frequency and applies the multiple phases to the divider circuit of the present invention. In a first embodiment, each phase is applied to a phase slip divider circuit which includes a integral divider portion and a programmable phase slip divider portion which receives the output of the integral division portion. Each phase of the input clock may therefore be divided by a wide variety of integral and non-integral divisors. In a second, simpler embodiment, a multi-phase frequency synthesizer produces a plurality of phases and applies the phases to a single phase slip divider.

Abstract: Provided is a technique for fabrication of STIs in a semiconductor device using implantation of damaging high-energy ions to insulating material overburden to generally and/or selectively increase insulation overburden removal rates. This technique avoids the use of chemical mechanical planarization (CMP) with a combination of implantation and, in some instances, low cost batch etching. The electrical characteristics of devices created with the new technique match closely to those fabricated with the standard CMP-based technique.